RT6204 Wide Vin Buck Converter

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<div class="tb-system"> <div class="WordSection1"> <h1>RT6204 Wide Vin Buck Converter</h1> <h2 id="__Bookmark__0">Abstract</h2> RT6204 is a flexible buck converter for wide input and output voltage range applications. It can be used with input voltages from 5.2V up to 60V and the output can be adjusted from 0.8V up to 50V, delivering up to 0.5A output currents. The application input and output voltage range should be considered when choosing the converter key components. This application note describes 4 different step-down designs, from 1.2V output to 24V output voltage. Each design shows all component calculations and measurement results over the full input voltage range. <div class="MsoNormal"> </div> </div> <div class="WordSection2"> <h2 id="__Bookmark__1">1. Introduction</h2> RT6204 is a flexible buck converter for wide input and output voltage range applications. It can be used with input voltages from 5.2V up to 60V and the output can be adjusted from 0.8V up to 50V, delivering up to 0.5A output currents. Chapter 2 provides an overview of the application component selection and design considerations. Chapters 3, 4, 5 and 6 each describe a design with specific VIN/VOUT condition from low 1.2V MCU supply to industrial supply providing 24V output. <h2 id="__Bookmark__2">2. RT6204 general design guidelines</h2> The RT6204 application schematic is shown in figure 1. RT6204 is a current mode converter with external compensation and external soft-start. The converter has both integrated high-side MOSFET switch and synchronous rectifier switch. The output can be set via a simple resistor divider. Current mode control with external compensation makes it possible to tune the converter control loop for a wide range of output capacitors, from low ESR ceramic types to aluminum electrolytic capacitors. This gives the designer the freedom to choose the most suitable and cost effective components for any output voltage application. <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image002_en.png" class="fancybox"> <img width="603" height="266" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image002_en.png" alt="Technical Document Image Preview" /></a> Figure 1 The following guidelines can be used to calculate the various application components: · Input and output voltage considerations: The RT6204 output voltage can be adjusted from 0.8V to 50V by means of R1 and R2: <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image003_en.png" class="fancybox"> <img width="121" height="26" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image003_en.png" alt="Technical Document Image Preview" id="圖片 33" /></a> The impedance of the feedback network is not critical, but it is recommended to avoid too high resistor values to reduce sensitivity to noise. It is recommended to set R2 between 10kΩ ~ 30kΩ. RT6204 has a low minimum on time of 90nsec, achieving minimum duty-cycle in CCM mode of 90nsec ‧ 350kHz = 3.15%. It should be noted that running the converter close to its minimum on time will influence output ripple and over-current protection behavior. This is explained in chapter 3. When operating RT6204 in high duty-cycles exceeding 65%, the external bootstrap supply via D1 should be added. The external bootstrap supply is recommended to be around 3.3~3.8V. (Below 3.5V D1 should preferably be a Schottky diode) · For Inductor value of L1 there are two main criteria that need to be considered: Inductor current ripple and slope compensation. For applications with duty-cycle lower than 50%, the inductor can be calculated to provide a ripple current of 30% of the IC 0.5A rated current (ΔIL = 150mA): <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image004_en.png" class="fancybox"> <img width="123" height="26" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image004_en.png" alt="Technical Document Image Preview" id="圖片 36" /></a> · In applications where the duty-cycle can exceed 50%, the inductor current falling slope dI/dt also needs to fit the converter internal slope compensation: L1 value needs to fulfill the following criteria: <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image005_en.png" class="fancybox"> <img width="56" height="23" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image005_en.png" alt="Technical Document Image Preview" id="圖片 37" /></a> µH · For output capacitor selection, there are several considerations: a. Output ripple in CCM mode Output ripple in CCM mode can be calculated from <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image006_en.png" class="fancybox"> <img width="239" height="26" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image006_en.png" alt="Technical Document Image Preview" id="圖片 38" /></a> The CCM mode inductor ripple can be calculated from: <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image007_en.png" class="fancybox"> <img width="158" height="26" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image007_en.png" alt="Technical Document Image Preview" id="圖片 40" /></a> When using ceramic output capacitors in these low voltage supplies, output ripple voltage in CCM mode will be small. b. Output ripple in PSM mode Output ripple in PSM mode will depend on the peak current in PSM mode and the load current. The worst case condition will happen at zero load: <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image008_en.png" class="fancybox"> <img width="321" height="26" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image008_en.png" alt="Technical Document Image Preview" id="圖片 41" /></a> RT6204 will regulate the inductor peak current in PSM mode around 150mA but there is around 80nsec propagation delay, so at high VIN and low VOUT the peak current will increase. PSM output voltage ripple will always be higher than CCM ripple. c. Voltage sag during load transients The voltage sag during a load transient in CCM mode depends on the load step, control loop speed and output capacitor. An approximate formula for voltage sag during a fast load step is shown below: <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image009_en.png" class="fancybox"> <img width="233" height="33" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image009_en.png" alt="Technical Document Image Preview" id="圖片 43" /></a> where ΔISTEP is the load step amplitude and FBW is the converter control bandwidth. Note that load step transitions between PSM and CCM mode operation will show higher voltage sag. Converter bandwidth is normally set around 1/10 of the switching frequency, except when using electrolytic capacitors: The ESR variation over temperature will require lower bandwidth setting to guarantee stable operation over the full temperature range. The converter bandwidth can be set via compensation resistor RCOMP. · Input capacitor considerations The input capacitor provides the high frequency switching current peaks of the converter. The input capacitor should be chosen to provide adequate filtering of the converter input, to minimize the VIN high frequency ripple. Low ESR ceramic capacitors should be placed close to the converter VIN and GND pins. At high input voltages, ceramic capacitors will have severely reduced capacitance, which should be considered when calculating the input ripple voltage. The peak-peak input ripple voltage can be approximated by: <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image010_en.png" class="fancybox"> <img width="157" height="26" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image010_en.png" alt="Technical Document Image Preview" id="圖片 48" /></a> where CIN is the capacitance at the DC input voltage. You will normally need at least 1µF capacitance and 100V rating, which will require 0805 or 1206 size MLCCs. Another consideration for the input capacitor is its RMS current rating: <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image011_en.png" class="fancybox"> <img width="183" height="33" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image011_en.png" alt="Technical Document Image Preview" id="圖片 51" /></a> The maximum RMS current will happen when VOUT is 50% of VIN. For the RT6204 maximum load current of 0.5A, the maximum RSM current in the input capacitor will be 0.25A. This value is normally not critical for ceramic capacitors with 0805 or 1206 size. If the converter requires hot-plugging into live input supplies, it is recommended to add a small electrolytic capacitor in parallel with the ceramic input capacitor. · Calculation of compensation components. The RT6204 compensation can use standard current mode type II compensation. The below simple formulas can be used: The compensator gain is set by RCOMP, and the value is calculated to provide a suitable converter crossover frequency (FC around 0.1 ‧ FSW) with sufficient phase margin. <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image012_en.png" class="fancybox"> <img width="149" height="26" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image012_en.png" alt="Technical Document Image Preview" id="圖片 52" /></a> Note that electrolytic output capacitors will require lower bandwidth, see chapter 5. The value of CCOMP is selected to set the compensation zero <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image013_en.png" class="fancybox"> <img width="106" height="26" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image013_en.png" alt="Technical Document Image Preview" id="圖片 53" /></a> a bit below the converter load pole <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image014_en.png" class="fancybox"> <img width="145" height="33" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image014_en.png" alt="Technical Document Image Preview" id="圖片 13" /></a> where RLOAD = VOUT/0.5A. The value for CP is chosen to set the high frequency pole at the output capacitor ESR zero: <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image015_en.png" class="fancybox"> <img width="87" height="26" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image015_en.png" alt="Technical Document Image Preview" id="圖片 56" /></a> When ceramic output capacitors are used, the ESR zero will lie at very high frequencies, above the converter switching frequency. For low VOUT applications with ceramic output capacitors, CP can be omitted. The feed-forward capacitor Cff is normally not needed for improving control loop response. But some small Cff capacitor can sometimes improve the PSM operation; by injecting some extra ripple on the FB pin double pulsing can be reduced. This can be tested case by case. · The soft-start capacitor sets the time tSS from EN high to VOUT reaching its final value which is defined by <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image016_en.png" class="fancybox"> <img width="74" height="26" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image016_en.png" alt="Technical Document Image Preview" id="圖片 57" /></a>. CSS is the value of the soft-start capacitor and ISS is the soft-start current (typically 6µA). VOUT starts rising when the VSS ramp passes 0.3V, and ends when VSS ramp passes 1.1V. The VOUT rise time can therefore be calculated by: <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image017_en.png" class="fancybox"> <img width="71" height="26" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image017_en.png" alt="Technical Document Image Preview" id="圖片 58" /></a>. Supplies with high output voltage and/or large value output capacitors should use sufficient soft-start time to avoid high inrush currents. · The converter can be enabled by pulling high the EN pin. The EN logic high level is typically 1.25V. There is a 1µA pull down current on EN. For automatic start-up when VIN is applied, the EN pin can be connected with a 100k pull-up resistor to VIN. The EN pin is 60V tolerant. <h2 id="__Bookmark__3">3. First Example application: 1.2V output </h2> In this first example we will design a converter with a fixed 1.2V output with a wide input voltage range. · Maximum input voltage: Based on minimum on time, the maximum input voltage for 1.2V output will be 1.2/0.0315 = 38V. In this 1.2V example we will examine how the minimum on time will influence output ripple and over-current protection performance. · Feedback network: use <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image018_en.png" class="fancybox"> <img width="121" height="26" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image018_en.png" alt="Technical Document Image Preview" id="圖片 59" /></a> to select R1 and R2: In this case we choose R1 = 7.5k and R2 = 15k which will give exactly 1.2V output. · Inductor value: For this 1.2 application, the duty-cycle will never reach 50%, so slope compensation is not critical in this case. Therefore, the inductor calculation can be purely based on ripple current. Using VIN = 38V, and current ripple of 0.3 ‧ 0.5A=0.15A: using <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image019_en.png" class="fancybox"> <img width="117" height="26" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image019_en.png" alt="Technical Document Image Preview" id="圖片 60" /></a> we find L = 22.1µH. At max 0.5A load, the inductor peak current will be (1+0.15) ‧ 0.5A = 0.575A. Normally the saturation current is chosen at least 10% higher than the maximum peak current, so Isat should be > 0.63A. For this example a Taiyo-Yuden NR6020T 22µH with Isat of 1A was chosen. · For output capacitor selection, we use the PSM ripple as selection criteria: First the PSM peak current is estimated: With VIN = 38V, VOUT = 1.2V, L = 22µH, the inductor current rising slope is (38-1.2)/22µH = 1.67A/µsec. 80nsec propagation delay will result in 0.133A current increase. The PSM peak current will therefore be around 280mA. For 1.2V output supply, we will use low ESR ceramic capacitors. The capacitor ESR can therefore be neglected, and the PSM ripple formula can be simplified: <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image020_en.png" class="fancybox"> <img width="246" height="26" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image020_en.png" alt="Technical Document Image Preview" id="圖片 61" /></a>. A worst case PSM ripple of 50mVpp requires 15.7µF capacitance. For this example two 10µF/16V 0805 X5R size MLCC output capacitors were selected: Murata GRM21BR61C106KE. The MLCC capacitance drop due to 1.2V dc bias voltage is very low and can be neglected. But MLCC capacitance is normally rated at an AC voltage of around 0.5Vrms. The capacitance will drop at lower AC RMS voltage. For this low voltage ripple application, a 27% capacitance drop must be considered. For more details on MLCC capacitor behavior, please see <a href="http://ds.murata.com/software/simsurfing/en-us/" class="link">http://ds.murata.com/software/simsurfing/en-us/</a> The total effective output capacitance becomes ~15µF output capacitance, which is used for further calculations. Measurements of the output ripple in PSM mode are shown in the figure 2 below: L1 = 22µH, COUT_eff = 15µF <table width="669" cellspacing="0" cellpadding="0" border="0" style="border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 17pt;"> <td style="width: 255.1pt; padding: 0cm 5.4pt; height: 17pt;"> VIN = 38V, VOUT = 1.2V, 1mA load </td> <td style="width: 246.75pt; padding: 0cm 5.4pt; height: 17pt;"> PSM ripple with 15µF capacitance is 46mVpp. </td> </tr> <tr style="height: 17pt;"> <td style="width: 255.1pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image021_en.jpg" class="fancybox"> <img width="319" height="240" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image021_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> </td> <td style="width: 246.75pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image022_en.jpg" class="fancybox"> <img width="318" height="241" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image022_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> </td> </tr> </tbody> </table> Figure 2 The effect of minimum ON time limit at high VIN is shown in the figure 3 below: (VOUT = 1.2V, 0.28A load) <table width="668" cellspacing="0" cellpadding="0" border="0" style="border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 17pt;"> <td style="width: 255.1pt; padding: 0cm 5.4pt; height: 17pt;"> VIN = 38V: Just full PWM, no pulse skipping </td> <td style="width: 246.05pt; padding: 0cm 5.4pt; height: 17pt;"> VIN = 42V: min ON time limit reached, pulse skipping </td> </tr> <tr style="height: 183.35pt;"> <td style="width: 255.1pt; padding: 0cm 5.4pt; height: 183.35pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image023_en.jpg" class="fancybox"> <img width="320" height="240" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image023_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> </td> <td style="width: 246.05pt; padding: 0cm 5.4pt; height: 183.35pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image024_en.jpg" class="fancybox"> <img width="320" height="240" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image024_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> </td> </tr> </tbody> </table> Figure 3 When the minimum ON time is reached in high VIN low VOUT applications, the converter will start skipping pulses to maintain regulated output. This pulse skipping will result in higher output voltage ripple. · For the input capacitor selection, the maximum allowed input ripple needs to be considered. The input capacitor also needs to have sufficient voltage rating. For 40V input range, a capacitor having least 60V voltage rating needs to be used. This normally means a ceramic capacitor with 100V rating. According <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image025_en.png" class="fancybox"> <img width="156" height="26" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image025_en.png" alt="Technical Document Image Preview" id="圖片 97" style="border-width: 0px; border-style: solid;" /></a> with 0.5A load current, 38V input and 1.2V output, 1µF of input capacitance means that the input ripple will be around 44mV ripple. It should be noted that this ripple does not include high frequency ringing due to capacitor ESL and layout ESL. In this example we used a small 100nF/100V 0603 X7R capacitor (Murata GRM188R72A104KA35) in parallel with a 2.2µF/100V 1206 X7R capacitor (Murata GRM31CR72A225KA73) which has an effective capacitance of 1.1µF at 38Vdc. <table cellspacing="0" cellpadding="0" border="0" style="border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 158.9pt;"> <td valign="top" style="width: 240.3pt; padding: 0cm 5.4pt; height: 158.9pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image026_en.jpg" class="fancybox"> <img width="305" height="228" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image026_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> </td> <td valign="top" style="width: 262.7pt; padding: 0cm 5.4pt; height: 158.9pt;"> Figure 4 shows the input ripple voltage measurement at 38V input and 0.5A load current. The ripple voltage shows a saw-tooth with 55mVpp amplitude, but there is also considerable high frequency noise present, due to parasitic ESL. To avoid this high frequency noise entering the input power lines, it is recommended adding additional filtering by means of a high frequency bead and extra capacitance. The worst case RMS current in the input capacitor for this application happens at the lowest input voltage (5.2V), and will be around 0.2A. This will not be a problem for the selected input capacitors. </td> </tr> <tr style="height: 9.35pt;"> <td valign="top" style="width: 240.3pt; padding: 0cm 5.4pt; height: 9.35pt;"> Figure 4 </td> <td valign="top" style="width: 262.7pt; padding: 0cm 5.4pt; height: 9.35pt;"> </td> </tr> </tbody> </table> · Calculation of compensation components. For the compensation component calculations we will use the formulas as given in chapter 2. For the output capacitance we use COUT_eff =15µF. <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image027_en.png" class="fancybox"> <img width="149" height="26" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image027_en.png" alt="Technical Document Image Preview" id="圖片 42" style="border-width: 0px; border-style: solid;" /></a> : With GmEA = 970µA/V, GCS = 0.9A/V and COUT_eff = 15µF: RCOMP becomes 5.7kΩ We will choose 5.6kΩ The converter load pole <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image028_en.png" class="fancybox"> <img width="146" height="32" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image028_en.png" alt="Technical Document Image Preview" id="圖片 62" style="border-width: 0px; border-style: solid;" /></a> lies at 4.4kHz. <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image029_en.png" class="fancybox"> <img width="160" height="31" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image029_en.png" alt="Technical Document Image Preview" id="圖片 63" style="border-width: 0px; border-style: solid;" /></a> = 6.4nF We will choose 6.8nF. The ceramic output capacitors will have a combined ESR of 2.5mΩ. The ESR zero lies at 4.2MHz. CP can be omitted. Converter stability was checked by means of fast load step, see figure 5. <table cellspacing="0" cellpadding="0" border="0" style="border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr> <td valign="top" style="width: 260.5pt; padding: 0cm 5.4pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image030_en.jpg" class="fancybox"> <img width="301" height="228" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image030_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> </td> <td valign="top" style="width: 260.5pt; padding: 0cm 5.4pt;"> Fast load step at 24V input shows stable performance without ringing. Converter sag at 250mA load step shows 74mV </td> </tr> <tr> <td valign="top" style="width: 260.5pt; padding: 0cm 5.4pt;"> Figure 5 </td> <td valign="top" style="width: 260.5pt; padding: 0cm 5.4pt;"> </td> </tr> </tbody> </table> · The soft-start capacitor sets the time tSS from EN high to VOUT reaching its final value which is defined by <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image031_en.png" class="fancybox"> <img width="80" height="26" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image031_en.png" alt="Technical Document Image Preview" id="圖片 153" style="border-width: 0px; border-style: solid;" /></a>. CSS is the value of the soft-start capacitor and ISS is the soft-start current (typically 6µA). For the 1.2V application with relatively small output capacitors, inrush current is not critical. CSS = 10nF gives a total start-up time of 1.83msec and VOUT rise time of 1.3msec. <table cellspacing="0" cellpadding="0" border="0" style="border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 158.9pt;"> <td valign="top" style="width: 240.3pt; padding: 0cm 5.4pt; height: 158.9pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image032_en.jpg" class="fancybox"> <img width="302" height="228" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image032_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> </td> <td valign="top" style="width: 262.7pt; padding: 0cm 5.4pt; height: 158.9pt;"> Figure 6 shows the soft-start behavior: When EN goes high, the soft-start ramp starts rising. The converter starts switching when the soft-start ramp passes 0.3V and VOUT rises. Switching frequency gradually increases as VOUT increases. When the soft-start ramp reaches 1.1V, the converter output reaches its final value. </td> </tr> <tr style="height: 9.35pt;"> <td valign="top" style="width: 240.3pt; padding: 0cm 5.4pt; height: 9.35pt;"> Figure 6 </td> <td valign="top" style="width: 262.7pt; padding: 0cm 5.4pt; height: 9.35pt;"> </td> </tr> </tbody> </table> · Over-current protection behavior: RT6204 has a cycle by cycle peak current limiting circuit that uses the high side MOSFET current sense. When the converter output loading is increased, at some point the peak current limit will be reached: the protection circuit will then reduce the high side MOSFET on time to avoid further current rise. <table cellspacing="0" cellpadding="0" border="0" style="border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 158.9pt;"> <td valign="top" style="width: 240.3pt; padding: 0cm 5.4pt; height: 158.9pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image033_en.jpg" class="fancybox"> <img width="304" height="228" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image033_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> </td> <td valign="top" style="width: 262.7pt; padding: 0cm 5.4pt; height: 158.9pt;"> Figure 7 shows the current limit measurement at VIN = 20V: When the inductor current reaches 950mA, the duty-cycle is reduced and VOUT starts to drop. The over current protection level of this 20V – 1.2V application is slightly higher than the datasheet OCP level due to the current sense propagation delay: (20-1.2)/22µH = 0.85A/µsec. 80nsec propagation delay will result in 0.068A current increase. When VOUT drops below the output under voltage protection (UVP level is 50% of VOUT), the converter shuts down, and an automatic soft-start cycle is initiated. </td> </tr> <tr style="height: 9.35pt;"> <td valign="top" style="width: 240.3pt; padding: 0cm 5.4pt; height: 9.35pt;"> Figure 7 </td> <td valign="top" style="width: 262.7pt; padding: 0cm 5.4pt; height: 9.35pt;"> </td> </tr> </tbody> </table> When the RT6204 converter is operating in high input voltage and low output voltage conditions and is subjected to overload situations, it is important to make sure that the converter’s minimum on-time does not prevent the current limit from operating properly. In minimum on time operation mode and overload condition, the converter will operate at the minimum duty and the output voltage will remain at whatever voltage that duty naturally produces. In this overloaded state the inductor current is no longer controlled and depends mainly on the load current, which eventually becomes high enough for the MOSFET and inductor component voltage drops to increase enough to allow VOUT to reach 50% and trigger UVP protection. <table width="671" cellspacing="0" cellpadding="0" border="0" style="width: 503pt; border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 158.9pt;"> <td valign="top" style="width: 241pt; padding: 0cm 5.4pt; height: 158.9pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image034_en.jpg" class="fancybox"> <img width="307" height="228" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image034_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> </td> <td valign="top" style="width: 262pt; padding: 0cm 5.4pt; height: 158.9pt;"> Figure 8 shows the current limit measurement at VIN = 40V: Due to propagation delay, the OC level now lies around 1.1A. The converter tries to reduce duty-cycle, but it is operating close to its minimum TON time. It can be seen that VOUT cannot drop much more and gets “stuck” around 830mV. The UVP level cannot be reached and the converter keeps operating in this maximum overload condition. When the converter load is further increased, the inductor current can actually increase beyond the over current limit. Any VOUT drop will now be caused by Rdson and inductor DCR drop, which may still trigger UVP protection. </td> </tr> <tr style="height: 3pt;"> <td valign="top" style="width: 241pt; padding: 0cm 5.4pt; height: 3pt;"> Figure 8 </td> <td valign="top" style="width: 262pt; padding: 0cm 5.4pt; height: 3pt;"> </td> </tr> </tbody> </table> When the RT6204 converter is operating in high input voltage and low output voltage conditions in combination with overload situations, it is important to check the minimum on time limitations. The complete 1.2V application is shown in figure 9. <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image035_en.jpg" class="fancybox"> <img width="604" height="210" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image035_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> Figure 9 <h2 id="__Bookmark__4">4. Second Example application: 5V output</h2> The second example explains the converter with a fixed 5V output with a wide input voltage range. · The maximum input voltage for this case is limited by the RT6204 60V maximum voltage rating: 5/60 = 8.3%, which is much larger than the RT6204 minimum duty-cycle of 3.15%. If the input supply can be lower than 7.5V, the duty-cycle will be higher than 65%, and the external bootstrap diode needs to be implemented. · Feedback network: use <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image036_en.png" class="fancybox"> <img width="131" height="31" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image036_en.png" alt="Technical Document Image Preview" id="圖片 34" style="border-width: 0px; border-style: solid;" /></a> to select R1 and R2: In this case we choose R1 = 43k and R2 = 8.2k which will give 4.995V output. · Inductor value: For this 5V application, the duty-cycle can exceed 50% when VIN is lower than 10V: for wide VIN applications, the effect of slope compensation on the minimum required inductance needs to be considered. The slope compensation criteria <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image037_en.png" class="fancybox"> <img width="98" height="27" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image037_en.png" alt="Technical Document Image Preview" id="圖片 54" style="border-width: 0px; border-style: solid;" /></a> requires an inductor greater than 83µH. Inductor calculation based on 30% current ripple at 60V input using <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image038_en.png" class="fancybox"> <img width="139" height="31" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image038_en.png" alt="Technical Document Image Preview" id="圖片 103" style="border-width: 0px; border-style: solid;" /></a> will give L = 87.3µH. In this example we will use 100µH. The selected inductor is a 100µH Wuerth Electronic 744066101 shielded inductor with a 1.2A saturation current and 0.255Ω resistance. · For output capacitor selection, we use the PSM ripple as selection criteria: First the PSM peak current is estimated: With VIN = 60V, VOUT = 5V, L = 100µH, the inductor current rising slope is (60-5)/100µH = 0.55A/µsec. 80nsec propagation delay will result in 0.044A current increase. The PSM max peak current will therefore be around 194mA. Note that at lower VIN, peak current increase due to propagation delay is very small, and the nominal 150mA PSM peak current can be used. For this 5V output supply, we will use low ESR ceramic capacitors. The capacitor ESR can therefore be neglected, and the PSM ripple formula will be: <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image039_en.png" class="fancybox"> <img width="285" height="33" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image039_en.png" alt="Technical Document Image Preview" id="圖片 143" style="border-width: 0px; border-style: solid;" /></a> At 60V input, a PSM ripple of 50mVpp requires around 9µF capacitance. For this example we used two 10µF/25V X5R 1206 size MLCC output capacitors, each having an effective capacitance of 6µF at 5Vdc bias and low AC ripple voltage. The effective capacitance becomes 12µF output capacitance, which is used for further calculations. Calculated PSM ripple at 60V input with 12µF output capacitance will be 37mVpp. <table cellspacing="0" cellpadding="0" border="0" style="border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 158.9pt;"> <td valign="top" style="width: 237.3pt; padding: 0cm 5.4pt; height: 158.9pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image040_en.jpg" class="fancybox"> <img width="291" height="219" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image040_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> </td> <td valign="top" style="width: 265.7pt; padding: 0cm 5.4pt; height: 158.9pt;"> Figure 10 shows the zero load PSM ripple for the 5V application with 60V input and 12µF effective output capacitance. PSM peak current and 39mVpp output ripple matches the calculated values quite well. </td> </tr> <tr style="height: 10.55pt;"> <td valign="top" style="width: 237.3pt; padding: 0cm 5.4pt; height: 10.55pt;"> Figure 10 </td> <td valign="top" style="width: 265.7pt; padding: 0cm 5.4pt; height: 10.55pt;"> </td> </tr> </tbody> </table> · For the input capacitor selection, the maximum allowed input ripple needs to be considered. The input capacitor also needs to have sufficient voltage rating. For 60V input range, a capacitor having least 90V voltage rating needs to be used. This normally means a ceramic capacitor with 100V rating. According <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image041_en.png" class="fancybox"> <img width="181" height="32" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image041_en.png" alt="Technical Document Image Preview" id="圖片 98" style="border-width: 0px; border-style: solid;" /></a> with 0.5A load current, 60V input and 5V output, 1µF of input capacitance gives input ripple will be around 110mV ripple. It should be noted that this ripple does not include high frequency ringing due to capacitor ESL and layout ESL. In this example we used a small 100nF/100V 0603 X7R capacitor (Murata GRM188R72A104KA35) in parallel with two pieces 2.2µF/100V 1206 X7R capacitor (Murata GRM31CR72A225KA73) each having an effective capacitance of 0.7µF at 60Vdc. The total combination of 1.5µF would give around 78mVpp calculated input ripple at 60Vdc input and 0.5A load. The worst case RMS current in the input capacitor in this 5V application will happen when VIN is 10V and the load is 0.5A. The maximum RMS current will be 0.25A; this will not be a problem for the selected input capacitors. <table cellspacing="0" cellpadding="0" border="0" style="border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 158.9pt;"> <td valign="top" style="width: 240.3pt; padding: 0cm 5.4pt; height: 158.9pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image042_en.jpg" class="fancybox"> <img width="293" height="219" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image042_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> </td> <td valign="top" style="width: 262.7pt; padding: 0cm 5.4pt; height: 158.9pt;"> Figure 11 shows the actual input ripple measurement, which shows 79mV saw-tooth input ripple. Additional high frequency noise is due to parasitic inductance. </td> </tr> <tr style="height: 9.35pt;"> <td valign="top" style="width: 240.3pt; padding: 0cm 5.4pt; height: 9.35pt;"> Figure 11 </td> <td valign="top" style="width: 262.7pt; padding: 0cm 5.4pt; height: 9.35pt;"> </td> </tr> </tbody> </table> · Calculation of compensation components. For the compensation component calculations we will use the formulas as given in chapter 2. For the output capacitance we use COUT_eff = 12µF. <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image043_en.png" class="fancybox"> <img width="175" height="33" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image043_en.png" alt="Technical Document Image Preview" id="圖片 100" style="border-width: 0px; border-style: solid;" /></a> : With GmEA = 970µA/V, GCS = 0.9A/V and COUT_eff = 12µF: RCOMP becomes 19kΩ. We will choose 18kΩ. The converter load pole <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image044_en.png" class="fancybox"> <img width="142" height="33" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image044_en.png" alt="Technical Document Image Preview" id="圖片 102" style="border-width: 0px; border-style: solid;" /></a> lies at 1.3kHz. <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image045_en.png" class="fancybox"> <img width="162" height="32" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image045_en.png" alt="Technical Document Image Preview" id="圖片 104" style="border-width: 0px; border-style: solid;" /></a> = 6.8nF. The ceramic output capacitors will have a combined ESR of 2.5mΩ. The ESR zero lies at 5.3MHz. CP calculation based on this ESR zero will be 1.6pF. But for higher output voltage application with larger duty-cycle variation, a larger value of CP is recommended. The datasheet recommended value of 47pF sets the compensator pole at 188kHz, which makes the converter operate more stable at higher duty-cycles at the expense of slightly lower overall phase margin. <table cellspacing="0" cellpadding="0" border="0" style="border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 158.9pt;"> <td valign="top" style="width: 240.3pt; padding: 0cm 5.4pt; height: 158.9pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image046_en.jpg" class="fancybox"> <img width="303" height="228" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image046_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> </td> <td valign="top" style="width: 262.7pt; padding: 0cm 5.4pt; height: 158.9pt;"> Figure 12 shows the output response with a fast load step from 200mA to 420mA. (Converter operating in CCM mode with an input voltage of 50V) The response is stable without ringing. Converter voltage sag at 220mA load step shows 90mV. </td> </tr> <tr style="height: 9.35pt;"> <td valign="top" style="width: 240.3pt; padding: 0cm 5.4pt; height: 9.35pt;"> Figure 12 </td> <td valign="top" style="width: 262.7pt; padding: 0cm 5.4pt; height: 9.35pt;"> </td> </tr> </tbody> </table> · For this 5V application with relatively small output capacitance, inrush current is not critical. The same 10nF soft-start capacitance as used for 1.2V application can be used, which gives total start-up time of 1.83msec based on: <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image047_en.png" class="fancybox"> <img width="94" height="30" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image047_en.png" alt="Technical Document Image Preview" id="圖片 126" style="border-width: 0px; border-style: solid;" /></a>. VOUT rise time from zero to 5V will be 1.3msec. · External Bootstrap capacitor charging circuit. If the converter input can be lower than 7.5V, the external bootstrap supply is needed. The optimal value for this bootstrap supply is around 3.3V: Higher values like 5V can lead to too strong high-side MOSFET drive which can lead to noise and unstable switching at certain conditions. The 3.3V bootstrap supply can be derived from the 5V output by using a zener voltage clamp. The average current that the external bootstrap circuit needs to supply is low, around 1mA max. The peak current in D1 is around 40mA max, and a small buffer capacitor can be used to supply this current. For the external bootstrap supply we will use zener clamp circuit: See figure 13. <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image048_en.jpg" class="fancybox"> <img width="361" height="100" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image048_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> Figure 13 To minimize the power needed for the circuit, the zener current is kept low, around 1mA. To compensate for the lower zener knee voltage at low current, a higher voltage zener diode is chosen, Vishay BZX384C3V9. Using a 680Ω bias resistor, at 5V output and 1mA bootstrap charging current, the current in the zener will be around 1.5mA with a zener clamping voltage of 3.5V. The total power dissipation in R3 is 2.5mA2 ‧ 680Ω = 4.25mW, so a small size SMD resistor can be used. The 47nF capacitor provides sufficient buffer for the 40mA D1 current pulses. When the converter goes into max duty-cycle dropout mode, VOUT will reduce and the external boot supply will drop to around 3.2V. This is still sufficient to drive the bootstrap supply. The figure 14 below shows the 5V converter operation at maximum load when VIN is reduced: The maximum duty-cycle is determined by the converter minimum off time which is around 200nsec, which results in 93% max duty-cycle. The input voltage where the converter reaches the max duty-cycle is heavily dependent on load current: The I ‧ Rdson drop and inductor I ‧ DCR drop need to be included, which is around 0.45V at 0.5A load. The VIN where drop-out starts to happen is then 5V/0.93 + 0.45V = 5.82V. <table width="688" cellspacing="0" cellpadding="0" border="0" style="border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 1cm;"> <td style="width: 172.1pt; padding: 0cm 5.4pt; height: 1cm;"> VIN = 10V: 50% duty-cycle VOUT = 5V </td> <td style="width: 172.1pt; padding: 0cm 5.4pt; height: 1cm;"> VIN = 6V: close to max duty-cycle: VOUT = 5V </td> <td style="width: 172.15pt; padding: 0cm 5.4pt; height: 1cm;"> VIN = 5V: dropout mode in max duty-cycle operation. VOUT = 4V </td> </tr> <tr style="height: 17pt;"> <td style="width: 172.1pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image049_en.jpg" class="fancybox"> <img width="211" height="159" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image049_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> </td> <td style="width: 172.1pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image050_en.jpg" class="fancybox"> <img width="212" height="159" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image050_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> </td> <td style="width: 172.15pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image051_en.jpg" class="fancybox"> <img width="212" height="159" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image051_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> </td> </tr> </tbody> </table> Figure 14 The total 5V application schematic is shown in figure 15. <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image052_en.jpg" class="fancybox"> <img width="750" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image052_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> Figure 15 <h2 id="__Bookmark__5">5. Third Example application: 12V output</h2> The third example analyzes the converter with a fixed 12V output and a wide input voltage range. · The maximum input voltage for the 12V output case is the same as for the 5V case: it is limited by the RT6204 60V maximum input voltage rating. If the input supply can be lower than 18.5V, the duty-cycle will be higher than 65%, and the external bootstrap charging circuit needs to be implemented. · Feedback network: use <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image053_en.png" class="fancybox"> <img width="131" height="30" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image053_en.png" alt="Technical Document Image Preview" id="圖片 154" style="border-width: 0px; border-style: solid;" /></a> to select R1 and R2: In this case we choose R1 = 140k and R2 = 10k as shown in the datasheet. · Inductor value: For this 12V application, the duty-cycle can exceed 50% when VIN is lower than 24V, so for wide VIN applications, the effect of slope compensation on the minimum required inductance needs to be considered. The slope compensation criteria <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image054_en.png" class="fancybox"> <img width="96" height="28" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image054_en.png" alt="Technical Document Image Preview" id="圖片 155" style="border-width: 0px; border-style: solid;" /></a> requires an inductor greater than 200µH. Inductor calculation based on 30% current ripple at 60V input using <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image055_en.png" class="fancybox"> <img width="136" height="31" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image055_en.png" alt="Technical Document Image Preview" id="圖片 156" style="border-width: 0px; border-style: solid;" /></a> gives L = 183µH. In this example we will use 220µH. The selected inductor is Bourns SRU1048A-221Y shielded inductor with a 0.7A saturation current and 0.455Ω resistance. · Output capacitor choice: For this 12V application you could either choose ceramic or electrolytic output capacitors. MLCC ceramic capacitors have considerable capacitance drop due to 12V dc bias, and you’ll need larger case size MLCC or several pieces in parallel to reach an effective capacitance above 10µF. For example, the 10µF/25V X5R 1206 size MLCC GRM31CR61E106KA12L will have around 2.9µF at 12Vdc and low ac ripple. Two pieces in parallel will give 5.8µF. A small SMD aluminum electrolytic capacitor of 47µF, 35V, 6.3x5.8mm size (like the Panasonic VFK Series) has an ESR of 0.36Ω and a rated RMS current of 240mA. You can calculate the output ripple for both types in PSM mode and CCM mode. The PSM peak current can be calculated in a similar way as the 5V example, and will be around 165mA for a 60V – 12V application with a 220µH inductor. The CCM ripple current will be around 124mApp. <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image056_en.png" class="fancybox"> <img width="382" height="43" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image056_en.png" alt="Technical Document Image Preview" id="圖片 157" style="border-width: 0px; border-style: solid;" /></a> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image057_en.png" class="fancybox"> <img width="490" height="41" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image057_en.png" alt="Technical Document Image Preview" id="圖片 158" style="border-width: 0px; border-style: solid;" /></a> PSM ripple at 60V input with 5.8µF MLCC output capacitance will be around 55mVpp. CCM ripple at 60V input with 5.8µF MLCC output capacitance will be around 8mVpp. PSM ripple at 60V input with 47µF electrolytic capacitor with 0.36Ω ESR will be around 59mVpp. CCM ripple at 60V input with 47µF electrolytic capacitor with 0.36Ω ESR will be around 46mVpp. As can be seen, the PSM output ripple for both types of capacitor are quite close, but MLCC capacitors will have lower ripple in CCM mode. But if you do the calculations at lower input voltage, you’ll find that the electrolytic capacitor will have lower PSM ripple than the MLCC capacitors. For this 12V output example, we will use the 47µF/35V 6.3x5.8mm electrolytic capacitor with ESR 0.36Ω. Figure 16 shows the measured output ripple in PSM mode and CCM mode when using this electrolytic output capacitor. <table width="669" cellspacing="0" cellpadding="0" border="0" style="border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 1cm;"> <td style="width: 250.9pt; padding: 0cm 5.4pt; height: 1cm;"> 12V output ripple in PSM mode with electrolytic capacitor: Ripple voltage is 46mVpp </td> <td style="width: 250.95pt; padding: 0cm 5.4pt; height: 1cm;"> 12V output ripple in CCM mode with electrolytic capacitor: Ripple voltage is 32mVpp </td> </tr> <tr style="height: 17pt;"> <td style="width: 250.9pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image058_en.jpg" class="fancybox"> <img width="319" height="240" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image058_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> </td> <td style="width: 250.95pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image059_en.jpg" class="fancybox"> <img width="318" height="240" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image059_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> </td> </tr> </tbody> </table> Figure 16 It should be noted that electrolytic capacitor ESR is heavily dependent on temperature: ESR becomes higher at lower temperatures. This effect should be included when the power supply has to operate at lower temperatures. It is recommended to place a small 100nF/50V ceramic capacitor in parallel with the electrolytic output capacitor: The low ESR ceramic capacitor will filter the high frequency spikes from the switching transitions. But this capacitor will not have any effect on the ripple amplitude or converter stability. · For the input capacitor selection we’ll use the same values as were used in the 5V output example: A small 100nF/100V 0603 X7R capacitor (Murata GRM188R72A104KA35) in parallel with two pieces 2.2µF/100V 1206 X7R capacitor (Murata GRM31CR72A225KA73) giving a total combination of 1.5µF. From <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image060_en.png" class="fancybox"> <img width="174" height="32" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image060_en.png" alt="Technical Document Image Preview" id="圖片 159" style="border-width: 0px; border-style: solid;" /></a> with a maximum 0.5A load current, 60V input and 12V output, 1.5µF of input capacitance will give an input ripple of around 152mVpp. The worst case RMS current in the input capacitor in this 12V application will happen when VIN is 24V and the load is 0.5A. The maximum RMS current will be 0.25A; this will not be a problem for the selected input capacitors. <table cellspacing="0" cellpadding="0" border="0" style="border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 158.9pt;"> <td valign="top" style="width: 240.3pt; padding: 0cm 5.4pt; height: 158.9pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image061_en.jpg" class="fancybox"> <img width="304" height="228" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image061_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> </td> <td valign="top" style="width: 262.7pt; padding: 0cm 5.4pt; height: 158.9pt;"> Figure 17 shows the actual input ripple measurement, which shows 142mV saw-tooth input ripple. Additional high frequency noise is due to parasitic inductance. </td> </tr> <tr style="height: 9.35pt;"> <td valign="top" style="width: 240.3pt; padding: 0cm 5.4pt; height: 9.35pt;"> Figure 17 </td> <td valign="top" style="width: 262.7pt; padding: 0cm 5.4pt; height: 9.35pt;"> </td> </tr> </tbody> </table> · Calculation of compensation components. For the compensation component calculations we will use the formulas as given in chapter 2. For the output capacitance we use COUT = 47µF and Output capacitor ESR = 0.36Ω. We will first use the standard bandwidth setting of 0.1 ‧ FSW: <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image062_en.png" class="fancybox"> <img width="171" height="32" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image062_en.png" alt="Technical Document Image Preview" id="圖片 160" style="border-width: 0px; border-style: solid;" /></a> : With GmEA = 970µA/V, GCS = 0.9A/V and COUT = 47µF: RCOMP becomes 178kΩ. We will choose 180kΩ. The converter load pole <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image063_en.png" class="fancybox"> <img width="143" height="34" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image063_en.png" alt="Technical Document Image Preview" id="圖片 161" style="border-width: 0px; border-style: solid;" /></a> lies at 141Hz. <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image064_en.png" class="fancybox"> <img width="159" height="35" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image064_en.png" alt="Technical Document Image Preview" id="圖片 162" style="border-width: 0px; border-style: solid;" /></a> = 6.3nF. We choose 6.8nF. The output capacitor ESR of 0.36Ω will result in an ESR zero of at 9.4kHz. From <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image065_en.png" class="fancybox"> <img width="105" height="32" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image065_en.png" alt="Technical Document Image Preview" id="圖片 163" style="border-width: 0px; border-style: solid;" /></a> we can find that CP needs to be 95pF. We’ll choose 100pF. Figure 18 show the step load response at room temperature, with a fast load step from 250mA to 500mA. <table width="680" cellspacing="0" cellpadding="0" border="0" style="border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 39.7pt;"> <td valign="top" style="width: 170.05pt; padding: 0cm 5.4pt; height: 39.7pt;"> 4msec step at 25oC: VOUT recovery time around 3msec due to RCOMP ‧ CCOMP time constant. </td> <td valign="top" style="width: 170.05pt; padding: 0cm 5.4pt; height: 39.7pt;"> 80µsec step shows the initial VOUT drop due output cap ESR. </td> <td valign="top" style="width: 6cm; padding: 0cm 5.4pt; height: 39.7pt;"> Zoom of ESR drop confirms the voltage drop to be ΔILOAD ‧ ESR (250mA ‧ 0.36Ω = 90mV) </td> </tr> <tr style="height: 17pt;"> <td style="width: 170.05pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image066_en.jpg" class="fancybox"> <img width="212" height="159" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image066_en.jpg" alt="TEK00035.PNG" id="Picture 98" style="border-width: 0px; border-style: solid;" /></a> </td> <td style="width: 170.05pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image067_en.jpg" class="fancybox"> <img width="212" height="159" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image067_en.jpg" alt="TEK00036.PNG" id="Picture 99" style="border-width: 0px; border-style: solid;" /></a> </td> <td style="width: 6cm; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image068_en.jpg" class="fancybox"> <img width="212" height="159" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image068_en.jpg" alt="TEK00037.PNG" id="Picture 100" style="border-width: 0px; border-style: solid;" /></a> </td> </tr> </tbody> </table> Figure 18 As mentioned earlier, electrolytic capacitor ESR is heavily dependent on temperature: ESR becomes much higher at lower temperatures. Below figure 19 show the step response at -20oC: <table width="680" cellspacing="0" cellpadding="0" border="0" style="margin-left: 16.6pt; border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 39.7pt;"> <td style="width: 170pt; padding: 0cm 5.4pt; height: 39.7pt;"> 4msec step at -20oC; Increased ripple. </td> <td style="width: 6cm; padding: 0cm 5.4pt; height: 39.7pt;"> 80µsec step at -20oC shows instability. </td> <td style="width: 6cm; padding: 0cm 5.4pt; height: 39.7pt;"> Zoom shows a voltage drop to be ΔILOAD ‧ ESR to be 316mV: ESR is now 316mV/250mA = 1.26Ω </td> </tr> <tr style="height: 17pt;"> <td style="width: 170pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image069_en.jpg" class="fancybox"> <img width="212" height="159" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image069_en.jpg" alt="TEK00041.PNG" id="Picture 107" style="border-width: 0px; border-style: solid;" /></a> </td> <td style="width: 6cm; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image070_en.jpg" class="fancybox"> <img width="212" height="159" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image070_en.jpg" alt="TEK00040.PNG" id="Picture 106" style="border-width: 0px; border-style: solid;" /></a> </td> <td style="width: 6cm; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image071_en.jpg" class="fancybox"> <img width="212" height="159" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image071_en.jpg" alt="TEK00039.PNG" id="Picture 105" style="border-width: 0px; border-style: solid;" /></a> </td> </tr> </tbody> </table> Figure 19 Clearly the converter is not stable at lower temperatures. What happened is that the increased output capacitor ESR at low temperature sets the modulator ESR zero at much lower frequency, around 2.6kHz. This increases the modulator gain at high frequencies and results in a much higher control bandwidth. The phase margin will be poor. To overcome this problem the compensation needs to be adjusted: You could just increase the value of CP, but this will reduce phase margin at room temperature ESR. It is better to reduce the overall converter bandwidth by reducing RCOMP considerably. This will give the best phase margin in both high ESR (low temperature) and low ESR (high temperature) condition. In this case we lower the bandwidth with a factor 3 to around 13kHz: RCOMP becomes 68k. CCOMP now becomes 15nF. Calculate CP for room temperature ESR of 0.36Ω: CP becomes 250pF, choose 270pF. The figure 20 below show the result: The step load response now looks good at both low temperature and high temperature conditions. <table width="671" cellspacing="0" cellpadding="0" border="0" style="border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 17pt;"> <td style="width: 167.75pt; padding: 0cm 5.4pt; height: 17pt;"> Load step at +25oC : OK </td> <td style="width: 167.75pt; padding: 0cm 5.4pt; height: 17pt;"> Load step at -30oC : OK </td> <td style="width: 167.75pt; padding: 0cm 5.4pt; height: 17pt;"> Load step at +70oC : OK </td> </tr> <tr style="height: 17pt;"> <td style="width: 167.75pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image072_en.jpg" class="fancybox"> <img width="212" height="159" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image072_en.jpg" alt="TEK00043.PNG" id="Picture 111" style="border-width: 0px; border-style: solid;" /></a> </td> <td style="width: 167.75pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image073_en.jpg" class="fancybox"> <img width="212" height="159" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image073_en.jpg" alt="TEK00042.PNG" id="Picture 112" style="border-width: 0px; border-style: solid;" /></a> </td> <td style="width: 167.75pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image074_en.jpg" class="fancybox"> <img width="212" height="159" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image074_en.jpg" alt="TEK00044.PNG" id="Picture 113" style="border-width: 0px; border-style: solid;" /></a> </td> </tr> </tbody> </table> Figure 20 · Soft-start design: For the 12V application with 47µF output capacitance, too fast VOUT rise time can result in some inrush current: To keep the inrush during VOUT rise less than 100mA, the rise time must be greater than 47µF ‧ 12V/100mA = 5.6msec. <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image075_en.png" class="fancybox"> <img width="80" height="31" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image075_en.png" alt="Technical Document Image Preview" id="圖片 164" style="border-width: 0px; border-style: solid;" /></a> , so CSS needs to be larger than 42nF. We will choose 47nF. This gives total start-up time of 8.6msec and VOUT rise time from 0 to 12V will be 6.3msec. <table cellspacing="0" cellpadding="0" border="0" style="border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 158.9pt;"> <td valign="top" style="width: 237.3pt; padding: 0cm 5.4pt; height: 158.9pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image076_en.jpg" class="fancybox"> <img width="303" height="228" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image076_en.jpg" alt="Technical Document Image Preview" id="Picture 26" style="border-width: 0px; border-style: solid;" /></a> </td> <td valign="top" style="width: 265.7pt; padding: 0cm 5.4pt; height: 158.9pt;" colspan="2"> Figure 21 shows the soft-start behavior of the 12V application. </td> </tr> <tr style="height: 9.35pt;"> <td valign="top" style="width: 240.3pt; padding: 0cm 5.4pt; height: 9.35pt;" colspan="2"> Figure 21 </td> <td valign="top" style="width: 262.7pt; padding: 0cm 5.4pt; height: 9.35pt;"> </td> </tr> <tr height="0"> <td style="border: medium none; width: 316px;"> </td> <td style="border: medium none; width: 4px;"> </td> <td style="border: medium none; width: 350px;"> </td> </tr> </tbody> </table> · External Bootstrap capacitor charging circuit. If the converter input can be lower than 18.5V, the external bootstrap supply is needed. The optimal value for this bootstrap supply is around 3.3V: Higher values like 5V can lead to too strong high-side MOSFET drive which can lead to noise and unstable switching at certain conditions. The 3.3V bootstrap supply can derived from the 12V output by using a zener voltage clamp similar to the 5V application. With an average bootstrap charge current of 1mA and a zener bias current of 1.5mA, the zener bias resistor R3 becomes (12V-3.3V)/2.5mA = 3.5k. We will choose 3.3k. The total power dissipation in R3 is 2.5mA2 ‧ 3.3kΩ = 20mW, so a small size SMD resistor can be used. The circuit is shown in figure 22. <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image077_en.jpg" class="fancybox"> <img width="378" height="106" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image077_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> Figure 22 Figure 23 below shows the 12V converter operation at maximum load when VIN is reduced: The maximum duty-cycle is determined by the converter minimum off time which is around 200nsec, which results in 93% max duty-cycle. The input voltage where the converter reaches the max duty-cycle depends on load current: The I ‧ Rdson drop and inductor I ‧ DCR drop need to be included, which is around 0.66V at 0.5A load for the 12V application. The VIN where drop-out starts to happen is then 12V/0.93 + 0.66V = 13.56V. <table width="688" cellspacing="0" cellpadding="0" border="0" style="border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 1cm;"> <td style="width: 170pt; padding: 0cm 5.4pt; height: 1cm;"> VIN = 15V: ~80% duty-cycle VOUT = 12V </td> <td style="width: 6cm; padding: 0cm 5.4pt; height: 1cm;"> VIN = 13.3V: just at max duty-cycle: VOUT = 12V </td> <td style="width: 176.25pt; padding: 0cm 5.4pt; height: 1cm;"> VIN = 10.1V: dropout mode in max duty-cycle operation. VOUT = 9.06V </td> </tr> <tr style="height: 17pt;"> <td style="width: 170pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image078_en.jpg" class="fancybox"> <img width="211" height="159" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image078_en.jpg" alt="Technical Document Image Preview" id="Picture 29" style="border-width: 0px; border-style: solid;" /></a> </td> <td style="width: 6cm; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image079_en.jpg" class="fancybox"> <img width="211" height="159" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image079_en.jpg" alt="Technical Document Image Preview" id="Picture 32" style="border-width: 0px; border-style: solid;" /></a> </td> <td style="width: 176.25pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image080_en.jpg" class="fancybox"> <img width="212" height="159" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image080_en.jpg" alt="Technical Document Image Preview" id="Picture 35" style="border-width: 0px; border-style: solid;" /></a> </td> </tr> </tbody> </table> Figure 23 The total 12V application schematic is shown in figure 24. <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image081_en.jpg" class="fancybox"> <img width="800" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image081_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> Figure 24 <h2 id="__Bookmark__6">6. Fourth Example application: 24V output</h2> This fourth example examines the converter with a fixed 24V output and a wide input voltage range. · The maximum input voltage for the 24V output case is the same as for the 12V case: it is limited by the RT6204 60V maximum input voltage rating. If the input supply can be lower than 37V, the duty-cycle will be higher than 65%, and the external bootstrap charging circuit needs to be implemented. · Feedback network: use <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image082_en.png" class="fancybox"> <img width="132" height="31" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image082_en.png" alt="Technical Document Image Preview" id="圖片 165" style="border-width: 0px; border-style: solid;" /></a> to select R1 and R2: In this case we choose R2 = 10k and R1 = 290k. · Inductor value: For this 24V application, the duty-cycle can exceed 50% when VIN is lower than 48V, so for wide VIN applications, the effect of slope compensation on the minimum required inductance needs to be considered. The slope compensation criteria <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image083_en.png" class="fancybox"> <img width="67" height="30" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image083_en.png" alt="Technical Document Image Preview" id="圖片 166" style="border-width: 0px; border-style: solid;" /></a> (µH) requires an inductor greater than 400µH. Inductor calculation based on 30% current ripple at 60V input using <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image084_en.png" class="fancybox"> <img width="136" height="31" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image084_en.png" alt="Technical Document Image Preview" id="圖片 167" style="border-width: 0px; border-style: solid;" /></a> gives L = 274µH. So we need to select the inductor based on slope compensation criteria. In this example we will use 470µH. The selected inductor is Bourns SSR1240-471 shielded inductor with a 0.6A saturation current and 1.35Ω resistance. · Output capacitor choice: For this 24V application, MLCC ceramic capacitors are not really suitable due to their large capacitance drop at high DC bias voltage. To achieve sufficient capacitance, you’d need large size 50V MLCC types, which are quite expensive. Small SMD aluminum electrolytic capacitors are more suitable. In the 12V output application we used 47µF, 35V, 6.3x5.8mm size (Panasonic VFK Series) with an ESR of 0.36Ω and a rated RMS current of 240mA. We can consider using this capacitor for the 24V application as well. You can calculate the output ripple in PSM mode and CCM mode. The PSM peak current for this 24V case will be the IC regulated PSM peak value of 150mA, without much propagation delay influence. The CCM ripple current with 470u inductor will be around 88mApp. <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image085_en.png" class="fancybox"> <img width="488" height="71" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image085_en.png" alt="Technical Document Image Preview" id="圖片 168" style="border-width: 0px; border-style: solid;" /></a> PSM ripple at 60V input with 47µF electrolytic capacitor with 0.36Ω ESR will be around 62mVpp. CCM ripple at 60V input with 47µF electrolytic capacitor with 0.36Ω ESR will be around 32mVpp. For this 24V output example, we will use the 47µF/35V 6.3x5.8mm electrolytic capacitor with ESR 0.36Ω. Figure 25 shows the measured output ripple in PSM mode and CCM mode when using this electrolytic output capacitor. It is recommended to place a small 100nF/50V ceramic capacitor in parallel with the electrolytic output capacitor: The low ESR ceramic capacitor will filter the high frequency spikes from the switching transitions. But this capacitor will not have any effect on the ripple amplitude or converter stability. <table width="670" cellspacing="0" cellpadding="0" border="0" style="border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 1cm;"> <td style="width: 255.1pt; padding: 0cm 5.4pt; height: 1cm;"> 24V output ripple in PSM mode with electrolytic capacitor: Ripple voltage is 82mVpp </td> <td style="width: 247.45pt; padding: 0cm 5.4pt; height: 1cm;"> 24V output ripple in CCM mode with electrolytic capacitor: Ripple voltage is 38mVpp </td> </tr> <tr style="height: 17pt;"> <td style="width: 255.1pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image086_en.jpg" class="fancybox"> <img width="317" height="240" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image086_en.jpg" alt="Technical Document Image Preview" id="Picture 41" style="border-width: 0px; border-style: solid;" /></a> </td> <td style="width: 247.45pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image087_en.jpg" class="fancybox"> <img width="318" height="240" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image087_en.jpg" alt="Technical Document Image Preview" id="Picture 44" style="border-width: 0px; border-style: solid;" /></a> </td> </tr> </tbody> </table> Figure 25 Input capacitor selection: The 24V application will have higher input ripple than the previous examples since the power level is higher. In the 12V application we used the 100nF/100V 0603 X7R capacitor (Murata GRM188R72A104KA35) in parallel with two pieces 2.2µF/100V 1206 X7R capacitor (Murata GRM31CR72A225KA73) giving a total combination of 1.5µF. If we use this same combination in the 24V application with 60V input and 0.5A load: <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image088_en.png" class="fancybox"> <img width="151" height="26" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image088_en.png" alt="Technical Document Image Preview" id="圖片 147" style="border-width: 0px; border-style: solid;" /></a> will give an input ripple of around 229mVpp. For EMC reasons, it may be necessary to add an additional 2.2µF/100V 1206 X7R and a high frequency bead. <table cellspacing="0" cellpadding="0" border="0" style="border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 158.9pt;"> <td valign="top" style="width: 240.3pt; padding: 0cm 5.4pt; height: 158.9pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image089_en.jpg" class="fancybox"> <img width="301" height="228" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image089_en.jpg" alt="Technical Document Image Preview" id="Picture 47" style="border-width: 0px; border-style: solid;" /></a> </td> <td valign="top" style="width: 262.7pt; padding: 0cm 5.4pt; height: 158.9pt;"> Figure 26 shows the actual input ripple measurement with the same 1.5µF input capacitor, resulting in a 230mVpp saw-tooth input ripple at 60V input and max 0.5A load. The worst case RMS current in the input capacitor in this 24V application will happen when VIN is 48V and the load is 0.5A. The maximum RMS current will be 0.25A. This will not be a problem for the selected input capacitors. </td> </tr> <tr style="height: 9.35pt;"> <td valign="top" style="width: 240.3pt; padding: 0cm 5.4pt; height: 9.35pt;"> Figure 26 </td> <td valign="top" style="width: 262.7pt; padding: 0cm 5.4pt; height: 9.35pt;"> </td> </tr> </tbody> </table> · Calculation of compensation components. As was shown in the 12V output application, the electrolytic output capacitor ESR variation over temperature can have a big impact on converter stability. If the converter has to work at very low temperatures, a factor 3 higher ESR has to be considered. Due to this effect, the converter bandwidth has to be set a factor 3 lower than the standard 0.1 ‧ FSW setting. For the 24V output supply, we will use similar bandwidth as the 12V application, around 12kHz instead of 35kHz. For the compensation component calculations we will use the formulas as given in chapter 2. For the output capacitance we use COUT = 47µF and output capacitor ESR = 0.36Ω. <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image090_en.png" class="fancybox"> <img width="167" height="34" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image090_en.png" alt="Technical Document Image Preview" id="圖片 105" style="border-width: 0px; border-style: solid;" /></a>: With GmEA = 970µA/V, GCS = 0.9A/V and COUT = 47µF: RCOMP becomes 124kΩ. We will choose 120kΩ. The converter load pole <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image091_en.png" class="fancybox"> <img width="144" height="32" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image091_en.png" alt="Technical Document Image Preview" id="圖片 123" style="border-width: 0px; border-style: solid;" /></a> lies at 71Hz. <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image092_en.png" class="fancybox"> <img width="155" height="33" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image092_en.png" alt="Technical Document Image Preview" id="圖片 124" style="border-width: 0px; border-style: solid;" /></a> = 18.7nF. We choose 18nF. We use the room temperature ESR to calculate CP: The output capacitor ESR of 0.36Ω will result in an ESR zero of at 9.4kHz. When we calculate <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image093_en.png" class="fancybox"> <img width="100" height="32" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image093_en.png" alt="Technical Document Image Preview" id="圖片 128" style="border-width: 0px; border-style: solid;" /></a> we can find that CP needs to be 136pF. We’ll choose a slightly larger value of 150pF. Figures 27 show the 250mA to 500mA step load response at +25oC (longer duration), and short duration pulse load steps at -30oC and +70oC to see the details of the transition. <table width="669" cellspacing="0" cellpadding="0" border="0" style="border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 17pt;"> <td style="width: 167.25pt; padding: 0cm 5.4pt; height: 17pt;"> 12msec load step at +25oC </td> <td style="width: 167.3pt; padding: 0cm 5.4pt; height: 17pt;"> 120µsec load step at -30oC : OK </td> <td style="width: 167.3pt; padding: 0cm 5.4pt; height: 17pt;"> 120µsec load step at +70oC : OK </td> </tr> <tr style="height: 17pt;"> <td style="width: 167.25pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image094_en.jpg" class="fancybox"> <img width="212" height="159" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image094_en.jpg" alt="TEK00059.PNG" id="Picture 23" style="border-width: 0px; border-style: solid;" /></a> </td> <td style="width: 167.3pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image095_en.jpg" class="fancybox"> <img width="212" height="159" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image095_en.jpg" alt="TEK00063.PNG" id="Picture 20" style="border-width: 0px; border-style: solid;" /></a> </td> <td style="width: 167.3pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image096_en.jpg" class="fancybox"> <img width="212" height="159" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image096_en.jpg" alt="TEK00060.PNG" id="Picture 21" style="border-width: 0px; border-style: solid;" /></a> </td> </tr> </tbody> </table> Figure 27 · Soft-start design: To keep the inrush current below 100mA for the 24V application with 47µF output capacitance, the VOUT rise time must be larger than 47µF ‧ 24V/100mA = 11msec. <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image097_en.png" class="fancybox"> <img width="81" height="29" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image097_en.png" alt="Technical Document Image Preview" id="圖片 127" style="border-width: 0px; border-style: solid;" /></a>, so CSS needs to be larger than 82nF. We will choose 100nF. VOUT rise time from 0 to 24V will be 13msec. <table cellspacing="0" cellpadding="0" border="0" style="border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 158.9pt;"> <td valign="top" style="width: 240.3pt; padding: 0cm 5.4pt; height: 158.9pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image098_en.jpg" class="fancybox"> <img width="303" height="228" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image098_en.jpg" alt="Technical Document Image Preview" style="border-width: 0px; border-style: solid;" /></a> </td> <td valign="top" style="width: 262.7pt; padding: 0cm 5.4pt; height: 158.9pt;"> Figure 28 shows the soft-start behavior of the 24V application. </td> </tr> <tr style="height: 9.35pt;"> <td valign="top" style="width: 240.3pt; padding: 0cm 5.4pt; height: 9.35pt;"> Figure 28 </td> <td valign="top" style="width: 262.7pt; padding: 0cm 5.4pt; height: 9.35pt;"> </td> </tr> </tbody> </table> · External Bootstrap capacitor charging circuit. If the converter input can be lower than 37V, the external bootstrap supply is needed. The optimal value for this bootstrap supply is around 3.3V: Higher values like 5V can lead to too strong high-side MOSFET drive which can lead to noise and unstable switching at certain conditions. The 3.3V bootstrap supply can derived from the 24V output by using a zener voltage clamp similar to the 12V application. With an average bootstrap charge current of 1mA and a zener bias current of 1.5mA, the zener bias resistor R3 becomes (24-3.3)/2.5mA = 8.2k. The total power dissipation in R3 is 2.5mA2 ‧ 8.2kΩ = 51mW, which may require a slightly larger size SMD resistor. The circuit is shown in figure 29. <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image099_en.jpg" class="fancybox"> <img width="387" height="107" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image099_en.jpg" alt="Technical Document Image Preview" id="Picture 5" style="border-width: 0px; border-style: solid;" /></a> Figure 29 Figure 30 below shows the 24V converter operation at maximum load when VIN is reduced: The maximum duty-cycle is determined by the converter minimum off time which is around 200nsec, which results in 93% max duty-cycle. The input voltage where the converter reaches the max duty-cycle depends on load current: The I ‧ Rdson drop and inductor I ‧ DCR drop need to be included, which is around 0.98V at 0.5A load for the 24V application. For the 24V application at 0.5A load current, the VIN where drop-out starts to happen is then 24V/0.93 + 0.98V = 26.8V. <table width="688" cellspacing="0" cellpadding="0" border="0" style="border-collapse: collapse; border: medium none;" class="MsoTableGrid"> <tbody> <tr style="height: 1cm;"> <td style="width: 172.1pt; padding: 0cm 5.4pt; height: 1cm;"> VIN = 33V: ~75% duty-cycle VOUT = 24.2V </td> <td style="width: 172.1pt; padding: 0cm 5.4pt; height: 1cm;"> VIN = 27.3V: just at max duty-cycle: VOUT = 24.2V </td> <td style="width: 172.15pt; padding: 0cm 5.4pt; height: 1cm;"> VIN = 25.2V: dropout mode in max duty-cycle operation. VOUT = 22.2V </td> </tr> <tr style="height: 17pt;"> <td style="width: 172.1pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image100_en.jpg" class="fancybox"> <img width="211" height="159" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image100_en.jpg" alt="Technical Document Image Preview" id="Picture 8" style="border-width: 0px; border-style: solid;" /></a> </td> <td style="width: 172.1pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image101_en.jpg" class="fancybox"> <img width="212" height="159" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image101_en.jpg" alt="Technical Document Image Preview" id="Picture 11" style="border-width: 0px; border-style: solid;" /></a> </td> <td style="width: 172.15pt; padding: 0cm 5.4pt; height: 17pt;"> <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image102_en.jpg" class="fancybox"> <img width="213" height="159" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image102_en.jpg" alt="Technical Document Image Preview" id="Picture 14" style="border-width: 0px; border-style: solid;" /></a> </td> </tr> </tbody> </table> Figure 30 The total 24V application schematic is shown in figure 31. <a href="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image103_en.jpg" class="fancybox"> <img width="750" src="/content/dam/richtek-eds/resources/application-notes/an049/html-images-en/image103_en.jpg" alt="Technical Document Image Preview" id="Picture 17" style="border-width: 0px; border-style: solid;" /></a> Figure 31 <h2 id="__Bookmark__7">7. Conclusion</h2> RT6204 buck converter can be successfully used in applications that require wide input range and wide output range. The external compensation and soft-start make it possible to tune the design for various types of output capacitors. Simple formulas can be used to determining the external key components and measured results match the calculated results quite well. </div> <div> <table width="850" cellspacing="0" cellpadding="0" border="1" style="border: medium none currentcolor; width: 637.5pt; border-collapse: collapse;" class="3-51"> <tbody> <tr> <td style="border-width: 1pt 1px 1px 1pt; border-style: solid; border-color: #009eb8; height: 17pt; padding-right: 5pt; padding-left: 5pt; background-image: url(e); background-attachment: scroll; background-repeat: repeat; background-size: auto auto; background-origin: padding-box; background-clip: border-box; background-color: #009eb8;" colspan="2"> Next Steps </td> </tr> <tr style="height: 17pt;"> <td style="border-width: 1pt 1px 1px 1pt; border-style: solid; border-color: #009eb8; height: 17pt; padding-right: 5pt; padding-left: 5pt; background-image: url(e); background-attachment: scroll; background-repeat: repeat; background-size: auto auto; background-origin: padding-box; background-clip: border-box; background-color: #ffffff;"> Richtek Newsletter </td> <td style="border-width: 1pt 1px 1px 1pt; border-style: solid; border-color: #009eb8; height: 17pt; padding-right: 5pt; padding-left: 5pt; background-image: url(e); background-attachment: scroll; background-repeat: repeat; background-size: auto auto; background-origin: padding-box; background-clip: border-box; background-color: #ffffff;"> <a target="_blank" href="/My%20Richtek/Newsletters" class="link"> Subscribe Richtek Newsletter</a> </td> </tr> <tr style="height: 17pt;"> <td style="border-width: 1pt 1px 1px 1pt; border-style: solid; border-color: #009eb8; height: 17pt; padding-right: 5pt; padding-left: 5pt; background-image: url(e); background-attachment: scroll; background-repeat: repeat; background-size: auto auto; background-origin: padding-box; background-clip: border-box; background-color: #ffffff;"> Download </td> <td style="border-width: 1pt 1px 1px 1pt; border-style: solid; border-color: #009eb8; height: 17pt; padding-right: 5pt; padding-left: 5pt; background-image: url(e); background-attachment: scroll; background-repeat: repeat; background-size: auto auto; background-origin: padding-box; background-clip: border-box; background-color: #ffffff;"> <a href="~/media/AN%20PDF/AN049_EN.ashx" class="link">Download PDF</a> </td> </tr> </tbody> </table> </div> </div>

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