Application and Definition of Thermal Resistances on Datasheet

1rem

rt-dark-800

headline-3

false

Application Note Name

false

basicInfoTitle

rt-dark-300

applicationNoteInfo

left

buttonDownload

text-with-icon

secondary

i18n(button-item.download.button-label)

i18n(button-item.download.button-link)

_self

false

btnAllApplicationNote

text-with-icon

secondary

i18n(button-item.all-application-note.button-label)

i18n(button-item.all-application-note.button-link)

_self

false

width

fixed-width

basicInfoSection

withLine

2rem

width

full-width

<div class="WordSection1"> <h1>Application and Definition of Thermal Resistances on Datasheet</h1> <h2 id="__Bookmark__0">Abstract</h2> Thermal issue has been a crucial topic for a long time since high power density and low cost requirements became popular. As a power engineer, the assessment of maximum allowable power dissipation of every component in the system is one of the most important topics when developing a brand new product with good reliability. Generally, each component has a specific thermal characteristics table, which can be found in the datasheet. There are many thermal resistance listed in the table, including θJA, θJB, θJC…etc. Most of these values are defined under the specific JEDEC standards. The JEDEC standards provide the common criteria for measuring the thermal resistances of an IC package, which can be used by the power engineer to compare the thermal (material) properties of different devices. However, thermal resistances based on JEDEC rules can’t be directly applied to actual applications because of different layout arrangements (number of layout layers, PCB thickness, number of thermal Vias and power traces routing...etc.). Many power engineers are looking for better dependable thermal resistances for estimating the temperature of each component in their real power system. Hence, the alternative thermal parameters named psi-(Ψ) are given on the datasheet. Unlike traditional thermal resistances (θJA, θJB, θJC…etc.), these psi- thermal parameters (ΨJB, ΨJC…etc.) are measured on an evaluation board (EVB) which is very similar to the actual application PCB layout. Therefore, power engineer can use these parameters to calculate the junction temperature once they know the power dissipation of the chip. It can greatly reduce the effort on dealing with thermal issues in a quick way. In this application note, the definition and applications of thermal resistances are addressed. Thermal resistances according to both JEDEC standard and real PCB conditions are introduced. Moreover, a simple example for describing the difference between these two parameters is given in the last section. <h2 id="__Bookmark__1">1. Thermal Resistances Defined by JEDEC Standards</h2> In this section, the definition and measurement process of thermal resistances (θJA, θJCx and θJB) are introduced separately. Based on different package types, there are many JEDEC PCB standards. The standards are summarized at the end of this section. <h3>1.1 θJA Thermal Resistances </h3> The thermal resistance θJA (Theta-JA) is the chip junction-to-ambient air thermal resistance measured in the convection environments described in JESD51-2. The value can be used to compare the thermal performance of different packages if all the test conditions listed in Table 1 are similar. The following formula can be used to define the value of θJA : <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image001_en.png" ><img width=107 height=50 id="圖片 3" src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image001_en.png" alt="Technical Document Image Preview"></a> Where P is the “TOTAL” power (heat) dissipated in the chip. TJ is the junction temperature after thermal balance. TA is the ambient temperature. The unit of θJA is in oC/W. The θJA value is sometimes used to estimate the junction temperature with combination of system ambient temperature in a specific application. However, these estimations are not accurate due to the JEDEC standardized test condition (EVB layout rules) won’t match the user’s application condition. Following is the measurement process for θJA. The power (heat) can flow through PCB and case top, although most of heat transfers from junction to board in this condition. The contacted board follows the layout rules as defined in JEDEC 51 standards. <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image002_en.png" ><img width=490 height=163 src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image002_en.png" alt="Technical Document Image Preview"></a> Figure 1. θJA Measurement Process <h3>1.2 θJCx Thermal Resistances</h3> The conduction thermal resistance θJCx (Theta-JCx) is measured with nearly all of the component power dissipation flowing through either the top or the bottom of the package. The “x” indicates the case surface where TCase is measured and through which all the heat is forced to flow during the θJCx measurement, “top” for the top surface or “bot” for the bottom surface. The values may be useful for comparing packages but the test conditions don’t generally match the user’s application. An exception is an application where nearly all of the component heat is flowing through the top of the package to a heat sink (i.e. via a metal mounting tab). θJC(Top) is representative of this application. The following formula can be used to define the value of θJCx : <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image003_en.png" ><img width=125 height=51 id="圖片 4" src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image003_en.png" alt="Technical Document Image Preview"></a> Where P is the “PART” of the chip power (heat) that flows from the junction to the “x” case surface. Ideally, during θJCx measurement, close to 100% of the power flows from the junction to the “x” case surface. TJ is the junction temperature after thermal balance. The unit of θJCx is in oC/W. Figures 2 and 3 show the measurement processes for θJC(Top) and θJC(Bottom) respectively. The power (heat) flows in these two cases are opposite. For example, the power can only flow through junction to case top in the measurement process of θJC(Top); on the other hand, the power can only flow through junction to case bottom in the measurement process of θJC(Bottom). <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image004_en.png" ><img width=557 height=298 src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image004_en.png" alt="Technical Document Image Preview"></a> Figure 2. θJC(Top) Measurement Process <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image005_en.png" ><img width=566 height=288 src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image005_en.png" alt="Technical Document Image Preview"></a> Figure 3. θJC(Bottom) Measurement Process <h3>1.3 θJB Thermal Resistances</h3> θJB is the junction-to-board thermal resistance where TBoard is the temperature measured on or near the component lead, using a 2s2p board, as described in JESD51-8. For a leaded package, the thermocouple is attached to the foot of a lead. For an area array surface mount package, the thermocouple is attached to a board trace within 1mm of the package body. The following formula can be used to define the value of θJB : <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image006_en.png" ><img width=109 height=51 id="圖片 6" src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image006_en.png" alt="Technical Document Image Preview"></a> Where P is the “PART” of the chip power (heat) that flows from the junction to the board. Ideally, approximately to 100% of the power flows from the junction to the board during θJB measurement using the test fixture specified in JESD51-8. TJ is the junction temperature after thermal balance. The unit of θJB is in oC/W. To measure θJB, convection from the top of the package is blocked and a cold plate is attached to the board’s far side opposite the package location. See Figure 4 as below. In the moment, most of heats are transferred via bottom board. <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image007_en.png" ><img width=624 height=249 src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image007_en.png" alt="Technical Document Image Preview"></a> <a name="_Ref12548035">Figure </a>4. Illustration of the process for measuring θJB <h3>1.4 Summary of JEDEC PCB Standards</h3> According to package type, there are six different PCB standards. JESD51-3 and JESD51-7 apply to leaded surface mount (SMT) packages like flip-chip and QFN packages, and define the 1s (one signal layer) and 2s2p (two signal layers and two power layers) test boards respectively. JESD51-5 extends the test boards to packages with direct thermal attach mechanisms like deep down-set exposed pad packages and thermally tabbed packages. Generally, this applies to the SMT boards defined in JESD51-3 and JESD51-7. JESD51-9 defines test boards for area array SMT packages like ball grid array (BGA) packages. Both 1s and 2s2p test boards are included, as well as the requirements for dealing with thermal balls and vias. JESD51-10 and JESD51-11 define test boards for through-hole leaded packages like pin grid array packages (PGAs). JESD51-10 covers perimeter leaded packages and JESD51-11 covers area array leaded packages. Both 1s and 2s2p test boards are included in both standards. Besides, JESD51-2A addresses the environmental conditions for different packages thermal measurement under nature convection. Table 1. JEDEC PCB Standards for Different Packages <table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0 width=0 style='width:510.2pt;border-collapse:collapse;border:none'> <tr style='height:17.0pt'> <td width=220 style='width:165.0pt;border:solid #009EB8 1.0pt;background: #009EB8;padding:0cm 5.4pt 0cm 5.4pt;height:17.0pt'> Package Type </td> <td width=119 style='width:89.55pt;border:solid #009EB8 1.0pt;border-left: none;background:#009EB8;padding:0cm 5.4pt 0cm 5.4pt;height:17.0pt'> JEDEC-standard </td> <td width=341 style='width:255.65pt;border:solid #009EB8 1.0pt;border-left: none;background:#009EB8;padding:0cm 5.4pt 0cm 5.4pt;height:17.0pt'> Topic </td> </tr> <tr style='height:1.0cm'> <td width=220 style='width:165.0pt;border:solid #009EB8 1.0pt;border-top: none;padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> All </td> <td width=119 style='width:89.55pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> JESD51-2A </td> <td width=341 style='width:255.65pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) </td> </tr> <tr style='height:51.0pt'> <td width=220 style='width:165.0pt;border:solid #009EB8 1.0pt;border-top: none;padding:0cm 5.4pt 0cm 5.4pt;height:51.0pt'> Leaded Surface Mount Packages </td> <td width=119 style='width:89.55pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:51.0pt'> JESD51-3 </td> <td width=341 style='width:255.65pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:51.0pt'> Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages </td> </tr> <tr style='height:1.0cm'> <td width=220 style='width:165.0pt;border:solid #009EB8 1.0pt;border-top: none;padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> Leaded Surface Mount Components </td> <td width=119 style='width:89.55pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> JESD51-7 </td> <td width=341 style='width:255.65pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages </td> </tr> <tr style='height:1.0cm'> <td width=220 style='width:165.0pt;border:solid #009EB8 1.0pt;border-top: none;padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> Packages with TP (thermal pad) </td> <td width=119 style='width:89.55pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> JESD51-5 </td> <td width=341 style='width:255.65pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> Extension of Thermal Test Board Standards for Packages with Direct Thermal Attachment Mechanisms </td> </tr> <tr style='height:1.0cm'> <td width=220 style='width:165.0pt;border:solid #009EB8 1.0pt;border-top: none;padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> Area Array Surface Mount Package </td> <td width=119 style='width:89.55pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> JESD51-9 </td> <td width=341 style='width:255.65pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> Test Boards for Area Array Surface Mount Package Thermal Measurements </td> </tr> <tr style='height:1.0cm'> <td width=220 style='width:165.0pt;border:solid #009EB8 1.0pt;border-top: none;padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> Through-hole mount perimeter leaded packages </td> <td width=119 style='width:89.55pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> JESD51-10 </td> <td width=341 style='width:255.65pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements </td> </tr> <tr style='height:1.0cm'> <td width=220 style='width:165.0pt;border:solid #009EB8 1.0pt;border-top: none;padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> Through-Hole Area Array Leaded Package </td> <td width=119 style='width:89.55pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> JESD51-11 </td> <td width=341 style='width:255.65pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> Test Boards for Through-Hole Area Array Leaded Package Thermal Measurements </td> </tr> </table> <h2 id="__Bookmark__2">2. Thermal Characterization Parameters Defined by EVB Standard</h2> Referring to JESD51-2A[1] for IC thermal test method environmental conditions, the thermal characterization parameters ΨJT (Psi-JT) and ΨJB (Psi-JB) are measured by IC manufactures in the same environments as θJA, as listed in Table 1. Literally, these characterization parameters are very close to the results measured on actual EVBs. However, for better approach to real condition, the results on EVBs are suggested to replace the values on JEDEC’s high conduction boards. Afterwards, users can apply the Ψ (Psi) equations to estimate the component junction temperature in their application by measuring a component temperature in the application environment and using the appropriate Ψ thermal characterization parameter. <h3>2.1 ΨJT Thermal Characterization Parameters</h3> ΨJT is the junction-to-top thermal characterization parameter where TTop is the temperature at the top center of the package. <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image008_en.png" ><img width=120 height=41 id="圖片 13" src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image008_en.png" alt="Technical Document Image Preview"></a> Where P is the “TOTAL” power (heat) dissipated in the chip. As shown in the Figure 5, the power may leave the chip through any thermal path, not just the top of the package. A thermal couple is attached to the top of case center to sense the case temperature. The unit of ΨJT is in oC/W. In practice, the ΨJT value will be much smaller than the θJC(Top) value since the actual heat flow from junction to case top is much less compared to the θJC(Top) measurement condition. <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image009_en.png" ><img width=538 height=182 src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image009_en.png" alt="Technical Document Image Preview"></a> <a name="_Ref12873992">Figure </a>5. ΨJT Measurement Process <h3>2.2 ΨJB Thermal Characterization Parameters</h3> ΨJB is the junction-to-board thermal characterization parameter where TBoard is the temperature measured on or near the component lead. For a leaded package, the thermocouple is attached to the foot of a lead. For an area array surface mount package, the thermocouple is attached to a board trace within 1mm of the package body. <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image010_en.png" ><img width=127 height=39 id="圖片 14" src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image010_en.png" alt="Technical Document Image Preview"></a> Where P is the “TOTAL” power (heat) dissipated in the chip. As shown in Figure 6, the power may leave the chip through any thermal path, not just the board. A thermal couple is attached to the foot of a lead to sense the board temperature. The unit of ΨJB is in oC/W. <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image011_en.png" ><img width=557 height=182 src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image011_en.png" alt="Technical Document Image Preview"></a> <a name="_Ref12874594">Figure </a>6. ΨJB Measurement Process of Leaded Package 2.2.1 Considerations for Board Temperature Measurement According to different types of package or footprints, the measuring position of board temperature (TBoard) should be considered. There are rules summarized as below for reference: a. Area array package (CSP, QFN) : < 1mm from the package edge (close to ground pin). b. Leaded package (SOP, TSOT) : < 1mm from the ground pin edge. c. Choose Rule : Left to Right, more ground pins to less ground pins, clockwise. <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image012_en.png" ><img width=548 height=158 id="圖片 139" src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image012_en.png" alt="Technical Document Image Preview"></a> Figure 7. Selection of Board Temperature Measurement for different Package Type <h2 id="__Bookmark__3">3. Decoupling of Thermal Resistance Network</h2> There are three methods for heat transfer : conduction, convection and radiation. When the temperature difference is generated, the heat will start to flow from high temperature to low temperature. While most of heat will select the medium with smallest thermal resistance, PCB conduction via solder to copper provides the route. An example of thermal resistance network for a chip mounted on PCB is shown in Figure 8. <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image013_en.png" ><img width=682 height=384 src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image013_en.png" alt="Technical Document Image Preview"></a> <a name="_Ref36212885">Figure </a>8. An Example of Thermal Resistance Network In Figure 8, there are many routes for heat to dissipate in a thermal system. Each route demonstrates an equivalent thermal resistance. In this diagram, they are named with θxy, where xy means the thermal dissipating route from node to node, like junction(J) to case(C), case(C) to ambient(A), solder paste(S) to board(B) etc. Ideally, the θ should be the thermal resistance for physical meaning which related to thermal characteristics of material. However, it’s hard to calculate a specific thermal resistance within a complicated thermal system. Frankly, it is a lumped sum of variety thermal parameters. A simplified thermal resistance network is shown in Figure 9. The symmetric rule of Ohm’s law and thermal resistances are adopted for calculation. <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image025_en.png" ><img width=600 src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image025_en.png" alt="Technical Document Image Preview"></a> Figure 9. A Simplified Thermal Resistance Network In the simplified thermal resistance network as shown in Figure 9, there are three synthesized nodes (S, L, B(Top)), where S is an integration of multiple nodes (S1, S2 and S3) standing for a solder paste node, L is an integration of multiple nodes (L1 and L2) standing for a lead-frame node, and B(Top) is an integration of multiple nodes (B1(Top) and B2(Top)) standing for a board node. The Psum is the total heat dissipated from chip’s die, it acts like a current flowing out of die to everywhere in the overall system. The Psum can flow to three routes (junction to case top, junction to case bottom, junction to lead-frame) during heat dissipation. Hence, the Psum distributes to each route depending on the thermal resistance value. According to the definition described in section1 and section2, the thermal resistance (θJC(Top)) defined by JEDEC and thermal characteristic parameter (ΨJC(Top)) defined by EVB can be calculated as below : <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image015_en.png" ><img width=225 height=200 id="圖片 8" src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image015_en.png" alt="Technical Document Image Preview"></a> And the junction temperature can be calculated as below : TJ = TC + ΨJC(Top) × Psum = TC + θJC(Top) × PJC(Top) It should be noticed that the θJC(Top) should be much larger than ΨJC(Top). Actually, ΨJC(Top) is an equivalent thermal characteristic parameter from junction to case top for a given system instead of real thermal resistance based on material properties. However, ΨJC(Top) is easier to use for temperature estimation in real condition because PJC(Top) is hard to calculate in real cases. <h2 id="__Bookmark__4">4. Example of Using Thermal Parameters to Estimate Junction Temperature</h2> For a given application, power engineers can calculate the power dissipation of each component in the system. Generally, each component has a maximum allowable operating temperature for reliability considerations. As depicted above, the thermal resistances (θJA, θJCx and θJB) are measured with the conditions of the specific power (heat) transferring direction or a fixed board layout. In real conditions, the power may leave the chip through any thermal path and the layout may not be like the JEDEC PCB, so the estimated junction temperature based on θJA, θJCx and θJB can’t be accurate. Due to the fact that the thermal path is not fixed, ΨJT or ΨJB values may be used with package top or board temperature measurements respectively to provide good junction temperature estimates. In the situation where the component power dissipation is not precisely known, the use of ΨJT may provide a more accurate TJ estimate. This is because the plastic top surface temperature of the component is generally closer to the junction temperature than the board temperature. Therefore, ΨJT is smaller than ΨJB and there is less absolute temperature prediction error. An application example is described as below : The RT6253A is a 3A synchronized step-down Buck converter. It is available in TSOT-23-6(FC) package. Since power MOSFETs are embedded inside the chip, thermal estimation is crucial to confirm the acceptable output power rating in case of overheating. The most important thing is keeping the die temperature under the recommended operating condition, which is normally 125°C. Generally, there are many thermal parameters listed in the product’s datasheet as in Table 2. Some parameters are measured based on JEDEC standards, like θJA, θJC(Top) and θJC(Bottom). However, these can’t be directly applied to calculate the junction temperature if ambient temperature or case top temperature or case bottom temperature are known. Because the board conditions are quite different between EVB and JEDEC standard board, and the heat flow of θJC(Top) and θJC(Bottom) measurements are regarded in singular direction, the calculated junction temperature may be far away from the real value. On the other hand, some parameters are measured under the customized EVB, like θJA(EVB), ΨJC(Top) and ΨJB. By measuring the ambient temperature or case top temperature or board temperature and using these parameters, the operating junction temperature can be predicted more accurately. For a given example application condition, VIN = 12V, VOUT = 1V, IOUT = 3A, TA = 25°C, the thermal measurement result by Fluke Ti450 is as shown in Figure 13. In this case, the maximum top case temperature of IC is 67.4°C and the board temperature at GND pin is 51.6°C. The measuring location of the board temperature is shown in Figure 12. There is a quick method to estimate the power dissipation of chip from thermal parameters as shown in Table 2. Due to ΨCA(Top) is equal to (θJA(EVB) - ΨJC(Top)), the power dissipation can be calculated from DTCA/ΨCA(Top), where both ΨJC(Top) and θJA(EVB) are measured on the EVB. Therefore, the power dissipation is calculated as (67.4-25)/(61-13.9) = 0.9W. The conversion efficiency of this example is 74.85%, the total converter power loss is 1.014W. Which means the residual power loss on inductor and PCB traces is around 0.114W. After that, the maximum junction temperature of IC can be calculated as TJ = (PD_IC x θJA(EVB)) + TA = (0.9W x 61°C/W) + 25°C = 79.9°C. On the other hand, it can also be calculated by ΨJB parameter, and the maximum junction temperature is TJ = (PD_IC x ΨJB) + TBOARD = (0.9W x 31.53°C/W) + 51.6°C = 79.98°C. In order to measure the actual junction temperature at PD = 0.9W, we can make use of the thermal characteristic of low-side MOSFET’s body diode in Buck converter IC’s. The experimental setup for diode method is shown in Figure 10. We apply a pulsating current with large duty cycle (DHeat) on the body diode. The high current with large duty cycle applied to this case is IF,Heat = 1.32A to achieve high power dissipation in the IC. The duty cycle low period (1-DHeat) has a low conduction current (for this case, the IF,B = 80mA) which is used to measure the body diode forward voltage and we use this value to estimate the junction temperature. The IF,B is determined according to the VF curve of low-side MOSFET’s body diode as shown in Figure 11(a). A small current at the breaking point is suggested to avoid self-heating and get enough IF tolerance. As a result, the average power dissipation on the chip is 0.9W, which can be calculated by following equation. <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image016_en.png" ><img width=381 height=30 id="圖片 12" src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image016_en.png" alt="Technical Document Image Preview"></a> Where VF,Heat is the diode forward voltage when conducting with IF,Heat and VF,HighT is the diode forward voltage when conducting with IF,B. The duty cycle of pulsating current is recommended to be 90%. As shown in Figure 14, because there is some undershoot of IF,B when diode forward current switches from high to low, the voltage at the beginning point of transition is not accurate. Hence, some prediction for V1 point is adopted depending on the linearity of cooling curve after IF is stable at 80mA, V2 point. Then the voltage at V1 point is around 0.633V. Besides, it should be noticed that V2 can’t be directly used for junction temperature estimation since there is some temperature drop after IF,B is stable. Finally, the maximum junction temperature can be calculated by following equation : <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image017_en.png" ><img width=224 height=55 id="圖片 15" src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image017_en.png" alt="Technical Document Image Preview"></a> Where TLow,T = 25°C, VF,LowT = 0.732V, VF,HighT = 0.6333V and TCD = 0.0018V/°C. The TJ is 79.83°C. VF,LowT is the diode forward voltage as conducting IF,B at TAmbient = TLow,T. TCD is the temperature coefficient of body diode forward voltage as shown in Figure 11(b) which can be measured in a temperature chamber. The result shows the junction temperature calculated by θJA(EVB), ΨJC(Top) and ΨJB are match quite well with the result achieved by conducting body diode to estimate the junction temperature. <div class="tb-system"> <table class=MsoTableGrid border=0 cellspacing=0 cellpadding=0 width=0 style='width:637.5pt;border-collapse:collapse;border:none'> <tr> <td width=421 valign=top style='width:252.8pt;padding:0cm 5.4pt 0cm 5.4pt'> <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image018_en.png" ><img width=309 height=236 id="圖片 21" src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image018_en.png" alt="Technical Document Image Preview"></a> </td> <td width=429 valign=top style='width:257.4pt;padding:0cm 5.4pt 0cm 5.4pt'> <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image019_en.png" ><img width=329 height=188 id="圖片 22" src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image019_en.png" alt="Technical Document Image Preview"></a> </td> </tr> </table> </div> <a name="_Ref38639333">Figure </a>10. Diode Method for Junction Temperature Measurement <div class="tb-system"> <table class=MsoTableGrid border=0 cellspacing=0 cellpadding=0 width=0 style='width:637.5pt;border-collapse:collapse;border:none'> <tr> <td width=425 valign=top style='width:254.85pt;padding:0cm 5.4pt 0cm 5.4pt'> <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image020_en.png" ><img width=190 height=151 id="圖片 27" src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image020_en.png" alt="Technical Document Image Preview"></a> (a) </td> <td width=425 valign=top style='width:254.85pt;padding:0cm 5.4pt 0cm 5.4pt'> <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image021_en.png" ><img width=225 height=151 id="圖片 28" src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image021_en.png" alt="Technical Document Image Preview"></a> (b) </td> </tr> </table> </div> <a name="_Ref38640119">Figure </a>11. MOSFET Body Diode Characteristic Curves On the other hand, if we would have used θJC(Top) or θJC(Bottom) for calculating the junction temperature, it would result in (0.9W x 88.7°C/W) + 25°C = 104.83°C, which is much higher than real value of 79.83°C. In principle neither θJC(Top) or θJC(Bottom) are suitable to predict the junction temperature because the actual heat flow does not follow a unique direction. <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image022_en.png" ><img width=427 height=302 id="圖片 16" src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image022_en.png" alt="Technical Document Image Preview"></a> <a name="_Ref15913740">Figure </a>12. Measuring Point of Board Temperature on RT6253A EVB <a name="_Ref15390782">Table </a>2. Thermal Parameters of RT6253A in TSOT-23-6(FC) Package <table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0 width=0 style='width:510.2pt;border-collapse:collapse;border:none'> <tr style='height:17.0pt'> <td width=465 colspan=2 style='width:331.45pt;border:solid #009EB8 1.0pt; background:#009EB8;padding:0cm 5.4pt 0cm 5.4pt;height:17.0pt'> Thermal Parameter </td> <td width=149 style='width:106.3pt;border:solid #009EB8 1.0pt;border-left: none;background:#009EB8;padding:0cm 5.4pt 0cm 5.4pt;height:17.0pt'> TSOT-23-6(FC) </td> <td width=66 style='width:46.95pt;border:solid #009EB8 1.0pt;border-left: none;background:#009EB8;padding:0cm 5.4pt 0cm 5.4pt;height:17.0pt'> Unit </td> </tr> <tr style='height:1.0cm'> <td width=127 style='width:90.45pt;border:solid #009EB8 1.0pt;border-top: none;padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> θJA </td> <td width=338 style='width:241.0pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> Junction-to-ambient thermal resistance (JEDEC standard) </td> <td width=149 style='width:106.3pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> 88.7 </td> <td width=66 rowspan=6 style='width:46.95pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> °C/W </td> </tr> <tr style='height:17.0pt'> <td width=127 style='width:90.45pt;border:solid #009EB8 1.0pt;border-top: none;padding:0cm 5.4pt 0cm 5.4pt;height:17.0pt'> θJC(Top) </td> <td width=338 style='width:241.0pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:17.0pt'> Junction-to-case (top) thermal resistance </td> <td width=149 style='width:106.3pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:17.0pt'> 76.9 </td> </tr> <tr style='height:17.0pt'> <td width=127 style='width:90.45pt;border:solid #009EB8 1.0pt;border-top: none;padding:0cm 5.4pt 0cm 5.4pt;height:17.0pt'> θJC(Bottom) </td> <td width=338 style='width:241.0pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:17.0pt'> Junction-to-case (bottom) thermal resistance </td> <td width=149 style='width:106.3pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:17.0pt'> 6 </td> </tr> <tr style='height:1.0cm'> <td width=127 style='width:90.45pt;border:solid #009EB8 1.0pt;border-top: none;padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> θJA(EVB) </td> <td width=338 style='width:241.0pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> Junction-to-ambient thermal resistance (specific EVB) </td> <td width=149 style='width:106.3pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:1.0cm'> 61 </td> </tr> <tr style='height:17.0pt'> <td width=127 style='width:90.45pt;border:solid #009EB8 1.0pt;border-top: none;padding:0cm 5.4pt 0cm 5.4pt;height:17.0pt'> ΨJC(Top) </td> <td width=338 style='width:241.0pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:17.0pt'> Junction-to-top characterization parameter </td> <td width=149 style='width:106.3pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:17.0pt'> 13.9 </td> </tr> <tr style='height:17.0pt'> <td width=127 style='width:90.45pt;border:solid #009EB8 1.0pt;border-top: none;padding:0cm 5.4pt 0cm 5.4pt;height:17.0pt'> ΨJB </td> <td width=338 style='width:241.0pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:17.0pt'> Junction-to-board characterization parameter </td> <td width=149 style='width:106.3pt;border-top:none;border-left:none; border-bottom:solid #009EB8 1.0pt;border-right:solid #009EB8 1.0pt; padding:0cm 5.4pt 0cm 5.4pt;height:17.0pt'> 31.53 </td> </tr> </table> <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image023_en.jpg" ><img width=423 height=290 id="Picture 5" src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image023_en.jpg" alt="Technical Document Image Preview"></a> <a name="_Ref15655072">Figure </a>13. Measurement of Thermal Image by Fluke Ti450 <a class="fancybox" href="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image024_en.jpg" ><img width=446 height=335 id="圖片 1" src="/content/dam/richtek-eds/resources/application-notes/an061/html-images-en/image024_en.jpg" alt="Technical Document Image Preview"></a> <a name="_Ref15656651">Figure </a>14. Measurement of Junction Temperature by Diode Method <h2 id="__Bookmark__5">5. Conclusions</h2> In this application note, the differences between definitions of thermal resistances of θJA, θJB, θJC based on JEDEC standard and psi- thermal parameters of ΨJB, ΨJC based on customized EVB and test condition are addressed. The direction of heat flows very different for the θJB, θJC and ΨJB, ΨJC. In practical conditions, the heat flow depends on the thermal conductivity of material and the heat may leave the chip through multiple thermal paths instead of only one path. Literally, thermal resistances of θJA, θJB, θJC can be applied to compare the thermal conductivity of different packages from different IC suppliers under a standardized environment. On the other hand, the ΨJB, ΨJC thermal parameters are very useful to quickly predict the junction temperature in the actual application operation. An actual application example of these parameters has been provided in the report. The result shows that using the psi- thermal parameters to calculate the junction temperature is much more accurate than when using the JEDEC thermal resistance values. <h2 id="__Bookmark__6">6. Reference</h2> [1] JESD51-2A, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) [2] JESD51-12, Guidelines for Reporting and Using Electronic Package Thermal Information [3] SPRA953B, Semiconductor and IC Package Thermal Metrics [4] SBVA025, Using New Thermal Metrics [5] RT6253A/B Datasheet <table style="width: 637.5pt; border-collapse: collapse; border: medium none;" class="3-51" border="1" cellpadding="0" cellspacing="0"> <tbody> <tr style="height: 17pt;"> <td style="border-width: 1pt 1px 1px 1pt; border-style: solid; border-color: #009eb8; background-color: #009eb8; background-image: url(e); background-repeat: repeat; background-attachment: scroll; background-clip: border-box; background-origin: padding-box; background-size: auto auto; padding-right: 5pt; padding-left: 5pt; height: 17pt;" colspan="2"> Next Steps </td> </tr> <tr style="height: 17pt;"> <td style="border-width: 1pt 1px 1px 1pt; border-style: solid; border-color: #009eb8; background-color: #ffffff; background-image: url(e); background-repeat: repeat; background-attachment: scroll; background-clip: border-box; background-origin: padding-box; background-size: auto auto; padding-right: 5pt; padding-left: 5pt; height: 17pt;"> Richtek Newsletter </td> <td style="border-width: 1pt 1px 1px 1pt; border-style: solid; border-color: #009eb8; background-color: #ffffff; background-image: url(e); background-repeat: repeat; background-attachment: scroll; background-clip: border-box; background-origin: padding-box; background-size: auto auto; padding-right: 5pt; padding-left: 5pt; height: 17pt;"> <a class="link" href="http://www.richtek.com/My%20Richtek/Newsletters" target="_blank">Subscribe Richtek Newsletter</a> </td> </tr> <tr style="height: 17pt;"> <td style="border-width: 1pt 1px 1px 1pt; border-style: solid; border-color: #009eb8; background-color: #ffffff; background-image: url(e); background-repeat: repeat; background-attachment: scroll; background-clip: border-box; background-origin: padding-box; background-size: auto auto; padding-right: 5pt; padding-left: 5pt; height: 17pt;"> Download </td> <td style="border-width: 1pt 1px 1px 1pt; border-style: solid; border-color: #009eb8; background-color: #ffffff; background-image: url(e); background-repeat: repeat; background-attachment: scroll; background-clip: border-box; background-origin: padding-box; background-size: auto auto; padding-right: 5pt; padding-left: 5pt; height: 17pt;"> <a class="link" href="~/media/AN%20PDF/AN061_EN.ashx">Download PDF</a> </td> </tr> </tbody> </table> </div>

false

i18n(article-attachment.related-product-list.title)

_ATTACHMENT_HIDDEN_FIELD_

related-products

_ATTACHMENT_HIDDEN_FIELD_

applicationNoteArticle

width

fixed-width

articleSection

application-note

true

relatedProductList

left

btnAllApplicationNote2

text-with-icon

secondary

i18n(button-item.all-application-note.button-label)

i18n(button-item.all-application-note.button-link)

_self

false

width

fixed-width

productListSection

100