Selecting an Linear Regulator (LDO)

• V _IN (min) > 2.5V : PMOS-type LDOs
• V _IN (min) > 1.0V : NMOS-type LDOs with voltage bias or internal charge pump

Fixed output voltage LDOs have the feedback network internally. Adjustable output LDOs use an external feedback network, which gives more flexibility. Some adjustable parts also have an internal feedback network, so they can be used as fixed output version as well.

The current capability relates directly to dropout voltage and power dissipation.

LDO controllers use external MOSFETs which can have larger current capability.

The power dissipation in the LDO is determined by the voltage drop (V_IN-V_OUT) across the LDO multiplied by the current passing through the LDO (I_OUT), which can be calculated from the formula P_D = (V_IN - V_OUT) * I_LOAD.

The below graph shows the allowed LDO voltage drop versus LDO current for specific power dissipation values.

Larger current or larger voltage drop across the LDO quickly leads to high device power dissipation. The LDO package needs to be able to handle this power dissipation.

Maximum allowed device power dissipation for SMD type LDOs depends on package, PCB layout and ambient temperature. You can calculate the allowed power dissipation by dividing the allowed temperature difference between junction and ambient by the thermal resistance between junction and ambient. The thermal resistance value θ_JA is shown in the datasheet, but keep in mind that this value is based on the JEDEC method, which can be slightly conservative.

Here are some practical power dissipation limits for various package types, based on a normal PCB layout with some extra copper connected to the package pins and thermal pad, a maximum PCB ambient temperature of 60°C, and maximum silicon die temperature of 125°C. If your ambient temperature is lower, the power dissipation can be higher. If your PCB is small, or there are other hot components nearby, the maximum power dissipation may be less.

Learn more about improving your thermal design in our tutorial video.

Duration : 5:00 (English, with user selectable subtitles)

LDOs are Low Dropout Linear regulators. It basically means that these devices can still regulate the output voltage, even when the input voltage is very close to the output voltage.

LDO dropout voltage is defined as the voltage drop across the regulator where the device can no longer regulate the output voltage.

Here is the basic circuit of an LDO with a P-channel MOSFET pass device. The MOSFET source is connected to VIN. To regulate the output voltage, the error amplifier controls the P-MOSFET gate voltage with respect to VIN, thereby controlling the MOSFET conduction level.

The LDO needs a certain amount of input to output voltage difference for regulation.

When the difference between input and output voltage becomes smaller, the MOSFET operation shifts toward the MOSFET Ohmic region toward the left in the MOSFET I/V curves.

In the Ohmic region, the MOSFET becomes resistive, and the error amplifier will pull the gate near ground level. At that point, the output voltage cannot be regulated anymore.

To maintain a well regulated LDO output voltage, you should make sure that the input voltage including ripple and tolerances is always higher than the output voltage + LDO dropout voltage.

Dropout curves as shown in the LDO datasheet show this dropout voltage as a function of output current and temperature.

These I/V curves basically represent the R _DS(ON) of the pass MOSFET.

Find out more LDO operation, dropout curves and a practical measurement example of the RT9187 dropout voltage vs. output current in our tutorial video.

Duration : 3:13 (English, with user selectable subtitles)

PSRR stands for power supply ripple rejection. The LDO PSRR value quantifies how well the LDO can reject input supply ripple at a certain frequency to keep the output voltage free of noise and ripple. In Richtek datasheets, PSRR is defined as the ripple attenuation ratio V_OUT/V_IN, therefore lower PSRR values are better.

The diagram shows the example of PSRR vs. frequency. At frequencies up to 10kHz, LDOs have high open loop gain, and can reject input ripple very well.

When frequency increases, the loop gain reduces due to the bandwidth limit of the LDO, and the PSRR curves rise. Higher LDO load pushes the load pole upwards, so the unity gain frequency at high load is also higher. In this example the LDO unity gain frequency is 300kHz at light load and 1MHz at high load, as can be seen from the peaks in the graph.

Above the unity gain frequency, the LDO is not able to actively remove ripple. The ripple attenuation at these very high frequencies is mostly caused by the LDO output capacitor and the LDO internal parasitic impedance.

Learn more about LDO PSRR and practical design tips for using a LDO as a ripple and noise filter in our tutorial video.

Duration : 4:19 (English, with user selectable subtitles)

The LDO quiescent current is the current that is consumed by the IC internal feedback control and drive circuits. It is normally measured by measuring the current that flows out of the LDO ground pin.

The Richtek Low I_Q LDO portfolio contains LDOs with quiescent currents down to 1μA, which extends battery lifetime considerably.

Richtek ultra low I_Q LDOs provide dynamic quiescent current control for obtaining the best performance in battery powered applications requiring long battery life and good dynamic load performance. The Low I_Q LDO RT9063 provides a stable 2.8V supply to the micro controller, and the LDO ground current stays relatively constant at 1μA in the low load range, thereby prolonging battery life.

But at higher load currents, the ground current increases to improve the dynamic behavior of the LDO; when a sudden high load is encountered, the internal control circuit uses more energy to ensure a tight regulation of the output voltage.

Find out more in our tutorial video.

Duration : 3:15 (English, with user selectable subtitles)