General Description
The Evaluation Board demonstrates the RT9492GQVF(2) to be designed for a highly-integrated 5A Buck-Boost switch mode battery charge management and system power path management device for 1-4 cell Li-Ion and Li-polymer battery. The low impedance power path optimizes switch-mode operation efficiency, reduces battery charging time and extends battery life during discharging phase. The I2C serial interface with charging and system settings makes the device a truly flexible solution.
Performance Specification Summary
Summary of the RT9492GQVF(2) Evaluation Board performance specificiaiton is provided in Table 1. The ambient temperature is 25°C.
Table 1. RT9492GQVF(2) Evaluation Board Performance Specification Summary
Specification
|
Test Conditions
|
Min
|
Typ
|
Max
|
Unit
|
Supply Input Voltage Range
|
|
3.6
|
--
|
24
|
V
|
Maximum Input Current
|
|
--
|
--
|
3.3
|
A
|
Maximum OTG Current
|
OTG mode
|
--
|
--
|
3.32
|
A
|
Maximum Output Current
|
(SW2), ISYS
|
--
|
--
|
5
|
A
|
Maximum Battery Voltage
|
|
--
|
--
|
18.8
|
V
|
Maximum Charge Current
|
|
--
|
--
|
5
|
A
|
Maximum Discharge Current
|
|
--
|
--
|
10
|
A
|
Power-up Procedure
Suggestion Required Equipments
- RT9492GQVF(2) Evaluation Board
- DC power supply capable of 24V, 3.3A
- Battery simulator capable of 18.8V, 10A
- Electronic load capable of 10A
- Oscilloscope
Quick Start Procedures
The Evaluation Board is fully assembled and tested. Follow the steps below to verify board operation. Do not turn on supplies until all connections are made. When measuring the output voltage ripple, care must be taken to avoid a long ground lead on the oscilloscope probe. Measure the output voltage ripple by touching the probe tip and ground ring directly across the last output capacitor.
1. Use jumpers on JP22 to JP29 to set battery cells and switching frequency for default charging profile.
Battery Cell (s)
|
Switching Frequency
|
Jumper No.
|
1S
|
1.5MHz
|
JP22
|
750kHz
|
JP23
|
2S
|
1.5MHz
|
JP24
|
750kHz
|
JP25
|
3S
|
1.5MHz
|
JP26
|
750kHz
|
JP27
|
4S
|
1.5MHz
|
JP28
|
750kHz
|
JP29
|
2. Use jumpers on JP1 and JP2 to connect ACDRV1 and ACDRV2 to the gate driver output from IC. If the external AC-RBFETs are not needed, use jumpers on JP3 and JP4 to bypass them and JP1 and JP2 should be used to connect ACDRV1 and ACDRV2 to GND.
3. Use a jumper on JP8 with Mid-Right side to connect SDRV to the gate driver output from IC. If the external ship FET is not needed, use a jumper on JP5 to bypass it and use JP8 with Mid-Left side to connect SDRV to the capacitor.
4. Use a jumper on JP18 (TS_NORMAL) or JP19 (TS_POTENTIOMETER) for setting TS pin configuration and JP12 for connecting to REGN as pull-up voltage.
5. Use a jumper on JP13 (500mA) or JP14 (1.5A) for ILIM setting and JP21 for controlling HIZ_EN.
6. Use a jumper on JP9 with Mid-Right side to connect BATTERY to BATP when the external Ship FET is adopted. If the external Ship FET is not needed, use a jumper on JP9 with Mid-Left side to connect BATP to VBAT.
7. Use a jumper on JP87 for connecting Type_C_IN on VAC1 or VAC2.
Proper measurement equipment setup and follow the procedure below.
1) With power off, connect input power and ground to VIN1 or VIN2 and PGND respectively.
2) With load off, connect electronic load to SYSTEM and PGND respectively.
3) With power off, connect power and ground to BATTERY and PGND respectively. Turn on battery simulator, then the device is powered up.
4) Use I2C to set registers for charging function and proper protection level.
5) Turn on the input power supply to start charging. Make sure that the power supply voltage is under OVP level.
6) Check the output charging current using a current meter.
7) Once the proper charging current is established observe the output voltage regulation, ripple voltage, efficiency and other performance.
8) For testing SYS load, turns on the electronic load and adjusts SYS current.
Detailed Description of Hardware
Headers Description and Placement

Carefully inspect all the components used in the EVB according to the following Bill of Materials table, and then make sure all the components are undamaged and correctly installed. If there is any missing or damaged component, which may occur during transportation, please contact our distributors or e-mail us at evb_service@richtek.com.
Test Points
The EVB is provided with the test points and pin names listed in the table below.
Test Point/
Pin Name
|
Function
|
VAC1
|
Input voltage for VAC1.
|
PGND
|
Ground.
|
VAC2
|
Input voltage for VAC2.
|
SYSTEM
|
Output voltage for sys.
|
BATTERY
|
Battery connection point.
|
SNS_BATP
|
External battery positive sense
|
PD1
|
USB TYPE-C port.
|
JP87
|
TYPE-C USB BUS tied to VAC1 or VAC2 jumper.
|
JP8
|
SDRV tied to SHIPFET or 1nF capacitor.
|
JP31
|
Pull up for I2C/INT/CE.
|
JP1
|
ACDRV1 tied to AC-RBFET1 or GND.
|
JP2
|
ACDRV2 tied to AC-RBFET2 or GND.
|
JP3
|
VAC1-VBUS short jumper.
|
JP4
|
VAC2-VBUS short jumper.
|
JP5
|
BAT-BATTERY short jumper.
|
JP9
|
BATP tied to BATTERY or BAT.
|
JP12
|
REGN for TS circuit pull high jumper.
|
JP13
|
Test resistence jumper with 500mA for ILIM_HZ function.
|
JP14
|
Test resistence jumper with 1.5A for ILIM_HZ function.
|
JP17
|
CE pull low jumper.
|
JP18
|
Test resistence jumper with TS_NORMAL for JEITA.
|
JP19
|
Test resistence jumper with TS_POTENTIOMETER for JEITA.
|
JP21
|
Test resistence jumper for ILIM_HZ function.
|
JP22
|
PROG resistence jumper for default set 1S_1.5MHz_2A ICHG.
|
JP23
|
PROG resistence jumper for default set 1S_750KHz_2A ICHG.
|
JP24
|
PROG resistence jumper for default set 2S_1.5MHz_2A ICHG.
|
JP25
|
PROG resistence jumper for default set 2S_750KHz_2A ICHG.
|
JP26
|
PROG resistence jumper for default set 3S_1.5MHz_1A ICHG.
|
JP27
|
PROG resistence jumper for default set 3S_750KHz_1A ICHG.
|
JP28
|
PROG resistence jumper for default set 4S_1.5MHz_1A ICHG.
|
JP29
|
PROG resistence jumper for default set 4S_750KHz_1A ICHG.
|
JP32
|
STAT_LED enable jumper.
|
CP1
|
VAC1-VBUS short pad.
|
CP2
|
VAC2-VBUS short pad.
|
CP4
|
BAT-BATTERY short pad.
|
S1
|
Button for exit ship mode or system reset.
|
Default Jumper Setting on EVB
Jumper
|
Description
|
JP1
|
Short ACDRV1 to _acdrv1.
|
JP2
|
Short ACDRV2 to _acdrv2.
|
JP8
|
Short SDRV to MOS.
|
JP9
|
Short BATP to BATTERY.
|
JP12
|
Short REGN to TS pull-up resistor.
|
JP18
|
Short TS to normal temperature resistor.
|
JP14
|
Short ILIM for 1.5A.
|
JP24
|
For 2 cell/1.5MHz setting.
|
Bill of Materials
fSW = 1.5MHz
|
Reference
|
Count
|
Part Number
|
Value
|
Description
|
Package
|
Manufacturer
|
U1
|
1
|
RT9492GQVF(2)
|
--
|
Switching charger
|
VQFN-29TL 4x4 (FC)
|
RICHTEK
|
C6, C8
|
2
|
GRM033R61C473KE84
|
47nF
|
Capacitor, Ceramic, 16V, X5R
|
C-0201
|
MURATA
|
C14, C15, C18, C32
|
4
|
0402B104K500CT
|
0.1µF
|
Capacitor, Ceramic, 50V, X7R
|
C-0402
|
WALSIN
|
C35
|
1
|
GRM155R60J475ME47D
|
4.7µF
|
Capacitor, Ceramic, 6.3V, X5R
|
C-0402
|
MURATA
|
C38, C39, C95, C96, C97
|
5
|
GRM188R61E106KA73
|
10µF
|
Capacitor, Ceramic, 25V, X5R
|
C-0603
|
MURATA
|
C41
|
1
|
0402B102K500CT
|
1nF
|
Capacitor, Ceramic, 50V, X7R
|
C-0402
|
WALSIN
|
C98, C99, C100, C101, C102
|
5
|
GRM188R6YA106MA73
|
10µF
|
Capacitor, Ceramic, 35V, X5R
|
C-0603
|
MURATA
|
D13
|
1
|
LNL-190SUG
|
--
|
LED_GREEN
|
LED-0603
|
LighTop
|
L2
|
1
|
PIMB063T-1R0MS-68
|
1µH
|
20%/6.7mΩ
|
L-7-4X6-8
|
CYNTEC
|
PD1
|
1
|
C-NBR2L-AK5322
|
--
|
USB TYPE-C 3.1
|
9.24x9.1mm
|
ADVANCED-CONNECTEK
|
Q1, Q2, Q3, Q4
|
4
|
AONR36366
|
--
|
MOS
|
DFN 3X3 EP
|
ALPHA & OMEGA SEMICONDUCTOR
|
Q6
|
1
|
AON7528
|
--
|
MOS
|
DFN 3.3X3.3 EP
|
ALPHA & OMEGA SEMICONDUCTOR
|
R15
|
1
|
WR06X1000FTL
|
100Ω
|
Resistor, Chip, 1/10W, 1%
|
R-0603
|
WALSIN
|
R18
|
1
|
CR-02FL6---5K1
|
5.1kΩ
|
Resistor, Chip, 1/16W, 1%
|
R-0402
|
VIKING
|
R20
|
1
|
RTT032553FTP
|
255kΩ
|
Resistor, Chip, 1/10W, 1%
|
R-0603
|
RALEC
|
R21
|
1
|
WR06X1273FTL
|
127kΩ
|
Resistor, Chip, 1/10W, 1%
|
R-0603
|
WALSIN
|
R23
|
1
|
WR06X1003FTL
|
100kΩ
|
Resistor, Chip, 1/10W, 1%
|
R-0603
|
WALSIN
|
R24
|
1
|
WR06X3012FTL
|
30.1kΩ
|
Resistor, Chip, 1/10W, 1%
|
R-0603
|
WALSIN
|
R25, R44, R45
|
3
|
WR04X1002FTL
|
10kΩ
|
Resistor, Chip, 1/10W, 1%
|
R-0402
|
WALSIN
|
R28
|
1
|
WR04X4701FTL
|
4.7kΩ
|
Resistor, Chip, 1/16W, 1%
|
R-0402
|
WALSIN
|
R29
|
1
|
WR06X3001FTL
|
3kΩ
|
Resistor, Chip, 1/10W, 1%
|
R-0603
|
WALSIN
|
R30
|
1
|
WR06X4701FTL
|
4.7kΩ
|
Resistor, Chip, 1/10W, 1%
|
R-0603
|
WALSIN
|
R31
|
1
|
RC0603FR-076K04L
|
6.04kΩ
|
Resistor, Chip, 1/10W, 1%
|
R-0603
|
YAGEO
|
R32
|
1
|
WR06X8201FTL
|
8.2kΩ
|
Resistor, Chip, 1/10W, 1%
|
R-0603
|
WALSIN
|
R33
|
1
|
WR06X1052FTL
|
10.5kΩ
|
Resistor, Chip, 1/10W, 1%
|
R-0603
|
WALSIN
|
R34
|
1
|
WR06X1372FTL
|
13.7kΩ
|
Resistor, Chip, 1/10W, 1%
|
R-0603
|
WALSIN
|
R35
|
1
|
RTT031742FTP
|
17.4kΩ
|
Resistor, Chip, 1/10W, 1%
|
R-0603
|
RALEC
|
R36
|
1
|
CR0603F27K0P05Z
|
27kΩ
|
Resistor, Chip, 1/10W, 1%
|
R-0603
|
EVER OHMS
|
S1
|
1
|
HTS6601H
|
--
|
SW-TACT-SWITCH
|
TACT-BTN
|
High-Tronics
|
Typical Applications
EVB Schematic Diagram



1. The capacitance values of the input and output capacitors will influence the input and output voltage ripple.
2. MLCC capacitors have degrading capacitance at DC bias voltage, and especially smaller size MLCC capacitors will have much lower capacitance.
Measure Result
Power-UP with AC_RB1, VAC1 Plug in
|
Charging in Buck Mode
|

|

|
Charging in Boost Mode
|
Charging in Buck-Boost Mode
|

|

|
Charging Enabled by CE Pin
|
Charging Disabled by CE Pin
|

|

|
1s Battery Charger Efficiency
|
2s Battery Charger Efficiency
|

|

|
3s Battery Charger Efficiency
|
4s Battery Charger Efficiency
|

|

|
Thermal Image at VIN = 15V, VBAT = 8V, ICHG = 2A
|

|
Note: When measuring the input or output voltage ripple, care must be taken to avoid a long ground lead on the oscilloscope probe. Measure the output voltage ripple by touching the probe tip directly across the output capacitor.
Evaluation Board Layout
Figure 1 to Figure 4 are RT9492GQVF(2) Evaluation Board layout. This board size is 101.6mm x 109.7mm and is constructed on four-layer PCB, outer layers with 1 oz. Cu and inner layers with 1 oz. Cu.

Figure 1. Top View (1st layer)

Figure 2. PCB Layout—Inner Side (2nd Layer)

Figure 3. PCB Layout—Inner Side (3rd Layer)

Figure 4. Bottom View (4th Layer)