Linear Regulator (LDO)


Richtek portfolio of linear regulator can support low-dropout, high PSRR, multiple output and DDR Vtt applications. With different package preference and input voltage range, you always can find suitable device from our product matrix.

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LDO Definition

The Low dropout linear regulator or LDO can be used in applications where you need to drop a higher input voltage to a lower output voltage at relatively moderate power levels. They are especially suitable in applications which require low noise, low current and which have a small difference between the input and output voltage.

LDO Features

LDOs regulate the output voltage by controlling the conduction of the pass element in a linear regulation. This linear regulation provides accurate, noise free output voltage which can quickly respond to load changes on the output. The key advantage of an LDO is its simplicity and low cost design with low noise and fast voltage conversion.

Video Find what Richtek can offer to accelerate your design time with this Richtek LDO Tutorial Video.
Duration : 5:27 (English, with user selectable subtitles)
However, compared to a switching regulator, an LDO has relatively low efficiency in applications with high VIN / VOUT ratio and power dissipation is more critical.

The linear regulation means that the voltage difference between input and output times the average load current is dissipated in the LDO pass element. Power Dissipation can be calculated as PD = (VIN - VOUT) * ILOAD, so big difference between VIN and VOUT with high load currents would lead to excessive dissipation.

Higher power dissipation requires LDOs in larger packages, which increases cost, PCB space and application heat. When LDO power dissipation exceeds ~ 0.8W, it is wise to look for alternatives like Buck converters.


When selecting an LDO, one should first consider the input and output voltage range, the LDO current capability and package dissipation capability. LDO dropout voltage is the minimum VIN - VOUT voltage where the device can regulate.

In micro power applications, (i.e. applications that need to run from a battery for several years) the LDO quiescent current IQ needs to be low to avoid unwanted battery drain. These applications need special low IQ LDOs.

In applications that require a very clean and low noise output voltage, low noise and good PSRR will be the LDO key selection criteria.

LDO regulators are typically used when:

  • converting a higher input voltage (VIN) into a lower output voltage (VOUT)
  • a very clean power supply is required or when the application is noise sensitive
  • the VIN/VOUT ratio is not very high, i.e. 3.3V to 2.5V
  • the application draws moderate current (up to ~ 1A)
  • The LDO power dissipation is limited, i.e. less than 0.8W

LDO Types

Below is simple explanation of LDO operation using two popular configurations based on pass element structures: LDOs with PMOS and NMOS pass elements.

For applications with VIN > 2.5V
(with external VBIAS or internal charge pump)
For applications with VIN > 1V


Here is the basic circuit of a PMOS LDO. It consists of a pass element Q1, a voltage reference and an error amplifier which controls the pass element. The error amplifier senses the output voltage via a resistor divider network.

In this drawing, the pass element is a P-channel MOSFET with the source connected to the input voltage.

The control loop is simple: The error amplifier controls the P-MOSFET gate to keep the voltage at the feedback pin at the same level as the voltage reference.

When the output voltage drops due to increased load or lower input voltage, the error amplifier lowers the gate voltage with respect to the source. This increases the conduction level of the P-MOSFET, and the output voltage rises again to the original regulated voltage.

In this configuration, the MOSFET can be controlled very close to the MOSFET ON level, which makes it possible to operate VIN very close to VOUT. But since the gate cannot be pulled lower than ground level, the input voltage must be high enough to allow sufficient headroom for the MOSFET gate-source voltage. To ensure sufficient MOSFET gate drive voltage, LDO's with P-MOSFET pass elements normally have a minimum input voltage requirement of around 2.5V.


In some applications you may want to drive an LDO from a very low voltage supply rail. In these cases, you need to select an LDO with an N-channel MOSFET pass element.

LDO's with N-channel MOSFET pass elements need to provide a gate drive which is higher than the output voltage. In order to make it possible to use very low input and output voltages, many N-MOSFET LDO's have a gate drive circuit that is supplied by an internal charge-pump or external bias voltage. This makes it possible to use these LDOs with very low input voltages, down to 1V.

N-MOSFETs also have better RDS(ON) than similar sized P-MOSFETs, so their drop-out voltage is also lower, making it possible to supply more current in low voltage drop applications.

Below is an example of an NMOS LDO which provides a clean and stable 1.0V supply from a low 1.5V supply rail. Due to the low voltage drop of only 0.5V across the LDO, it can deliver more current without excessive dissipation.

Technical Document Image Preview

LDO Selection Criteria

In order to select a right LDO, some key criteria are important to be considered.

VIN (min)

Is your input voltage able to drive the pass-element of LDO?
  • VIN (min) > 2.5V : PMOS-type LDOs
  • VIN (min) > 1.0V : NMOS-type LDOs with voltage bias or internal charge pump

VIN (max)

Which upper bound of input voltage fits for your application best?


Do you need an adjustable output voltage? Which method do you prefer?

Fixed output voltage LDOs have the feedback network internally. Adjustable output LDOs use an external feedback network, which gives more flexibility. Some adjustable parts also have an internal feedback network, so they can be used as fixed output version as well.


What is the current requirement of your application?

The current capability relates directly to dropout voltage and power dissipation.

LDO controllers use external MOSFETs which can have larger current capability.

Power Dissipation

What is the current requirement of your application?

The power dissipation in the LDO is determined by the voltage drop (VIN-VOUT) across the LDO multiplied by the current passing through the LDO (IOUT), which can be calculated from the formula

The below graph shows the allowed LDO voltage drop versus LDO current for specific power dissipation values.

Larger current or larger voltage drop across the LDO quickly leads to high device power dissipation. The LDO package needs to be able to handle this power dissipation.

Maximum allowed device power dissipation for SMD type LDOs depends on package, PCB layout and ambient temperature. You can calculate the allowed power dissipation by dividing the allowed temperature difference between junction and ambient by the thermal resistance between junction and ambient. The thermal resistance value θJA is shown in the datasheet, but keep in mind that this value is based on the JEDEC method, which can be slightly conservative.

Power Dissipation

Here are some practical power dissipation limits for various package types, based on a normal PCB layout with some extra copper connected to the package pins and thermal pad, a maximum PCB ambient temperature of 60°C, and maximum silicon die temperature of 125°C. If your ambient temperature is lower, the power dissipation can be higher. If your PCB is small, or there are other hot components nearby, the maximum power dissipation may be less.

Learn more about improving your thermal design in our tutorial video.

PSOP-8 package and SOT-23-5 package
Video Duration : 5:00 (English, with user selectable subtitles)

Dropout Voltage

LDOs need a certain minimum voltage drop to regulate correctly.

LDOs are Low Dropout Linear regulators. It basically means that these devices can still regulate the output voltage, even when the input voltage is very close to the output voltage.

LDO dropout voltage is defined as the voltage drop across the regulator where the device can no longer regulate the output voltage.

LDO Dropout Voltage Explained

Here is the basic circuit of an LDO with a P-channel MOSFET pass device. The MOSFET source is connected to VIN. To regulate the output voltage, the error amplifier controls the P-MOSFET gate voltage with respect to VIN, thereby controlling the MOSFET conduction level.

The LDO needs a certain amount of input to output voltage difference for regulation.

When the difference between input and output voltage becomes smaller, the MOSFET operation shifts toward the MOSFET Ohmic region toward the left in the MOSFET I/V curves.

In the Ohmic region, the MOSFET becomes resistive, and the error amplifier will pull the gate near ground level. At that point, the output voltage cannot be regulated anymore.

Dropout Voltage

To maintain a well regulated LDO output voltage, you should make sure that the input voltage including ripple and tolerances is always higher than the output voltage + LDO dropout voltage.

Dropout curves as shown in the LDO datasheet show this dropout voltage as a function of output current and temperature.

These I/V curves basically represent the RDS(ON) of the pass MOSFET.

Find out more LDO operation, dropout curves and a practical measurement example of the RT9187 dropout voltage vs. output current in our tutorial video.

Video Duration : 3:13 (English, with user selectable subtitles)


If your device is sensitive to supply ripple and noise, a low noise linear regulator is an ideal choice for this supply.

PSRR stands for power supply ripple rejection. The LDO PSRR value quantifies how well the LDO can reject input supply ripple at a certain frequency to keep the output voltage free of noise and ripple. In Richtek datasheets, PSRR is defined as the ripple attenuation ratio VOUT/VIN, therefore lower PSRR values are better.

LDO as ripple surpressor

The diagram shows the example of PSRR vs. frequency. At frequencies up to 10kHz, LDOs have high open loop gain, and can reject input ripple very well.

When frequency increases, the loop gain reduces due to the bandwidth limit of the LDO, and the PSRR curves rise. Higher LDO load pushes the load pole upwards, so the unity gain frequency at high load is also higher. In this example the LDO unity gain frequency is 300kHz at light load and 1MHz at high load, as can be seen from the peaks in the graph.

Above the unity gain frequency, the LDO is not able to actively remove ripple. The ripple attenuation at these very high frequencies is mostly caused by the LDO output capacitor and the LDO internal parasitic impedance.

Learn more about LDO PSRR and practical design tips for using a LDO as a ripple and noise filter in our tutorial video.

LDO as ripple & noise filter
Video Duration : 4:19 (English, with user selectable subtitles)

Ultra Low Quiescent Current (IQ)

Does your application need to run from a small battery cell for long periods? These applications often will run in sleep mode most of the time, and are only active for short periods. To minimize the power consumption in sleep mode, you need to select parts with very low quiescent current, and this is where Richtek ultra low IQ LDOs are really suitable.
PSRR vs. Frequency

The LDO quiescent current is the current that is consumed by the IC internal feedback control and drive circuits. It is normally measured by measuring the current that flows out of the LDO ground pin.

The Richtek Low IQ LDO portfolio contains LDOs with quiescent currents down to 1µA, which extends battery lifetime considerably.

Low I<sub>Q</sub> LDO typical application

Richtek ultra low IQ LDOs provide dynamic quiescent current control for obtaining the best performance in battery powered applications requiring long battery life and good dynamic load performance. The Low IQ LDO RT9063 provides a stable 2.8V supply to the micro controller, and the LDO ground current stays relatively constant at 1µA in the low load range, thereby prolonging battery life.

But at higher load currents, the ground current increases to improve the dynamic behavior of the LDO; when a sudden high load is encountered, the internal control circuit uses more energy to ensure a tight regulation of the output voltage.

Find out more in our tutorial video.

Video Duration : 3:15 (English, with user selectable subtitles)
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Additional Documents
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Power Management Introduction and Selection Guide 2018/05/16
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